Patents by Inventor Il-Seok Son

Il-Seok Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10367070
    Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Kimin Jun, Il-Seok Son, Paul B. Fischer
  • Patent number: 10236282
    Abstract: An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Kimin Jun, Il-Seok Son, Rajashree Baskaran, Paul B. Fischer
  • Publication number: 20180248012
    Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
    Type: Application
    Filed: September 24, 2015
    Publication date: August 30, 2018
    Applicant: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Kimin Jun, Il-Seok Son, Paul B. Fischer
  • Publication number: 20180233409
    Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 24, 2015
    Publication date: August 16, 2018
    Inventors: Il-Seok SON, Colin T. CARVER, Paul B. FISCHER, Patrick MORROW, Kimin JUN
  • Publication number: 20180219090
    Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 2, 2018
    Inventors: Patrick MORROW, Kimin JUN, Il-Seok SON, Donald W. NELSON
  • Patent number: 9721898
    Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Don Nelson, M. Clair Webb, Kimin Jun, Il-Seok Son
  • Patent number: 9490201
    Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Don Nelson, M. Clair Webb, Kimin Jun, Il-Seok Son
  • Publication number: 20160233206
    Abstract: An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.
    Type: Application
    Filed: December 18, 2013
    Publication date: August 11, 2016
    Applicant: Intel Corporation
    Inventors: PATRICK MORROW, KIMIN JUN, IL-SEOK SON, RAJASHREE BASKARAN, PAUL B. FISCHER
  • Publication number: 20140264739
    Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Inventors: Patrick Morrow, Don Nelson, Clair M. Webb, Kimin Jun, Il-Seok Son