Patents by Inventor Il Sik JANG

Il Sik JANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11462545
    Abstract: A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Il-Sik Jang, Ji-Hwan Park, Mi-Ri Lee, Bong-Seok Jeon, Yong-Soo Joung, Sun-Hwan Hwang
  • Patent number: 10910224
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Tae-Su Jang, Jin-Chul Park, Ji-Hwan Park, Il-Sik Jang, Seong-Wan Ryu, Se-In Kwon, Jung-Ho Shin, Dae-Jin Ham
  • Publication number: 20200411323
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: Tae-Su JANG, Jin-Chul PARK, Ji-Hwan PARK, Il-Sik JANG, Seong-Wan RYU, Se-In KWON, Jung-Ho SHIN, Dae-Jin HAM
  • Patent number: 10811260
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: October 20, 2020
    Assignee: SK hynix Inc.
    Inventors: Tae-Su Jang, Jin-Chul Park, Ji-Hwan Park, Il-Sik Jang, Seong-Wan Ryu, Se-In Kwon, Jung-Ho Shin, Dae-Jin Ham
  • Publication number: 20200161307
    Abstract: A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 21, 2020
    Inventors: Il-Sik JANG, Ji-Hwan PARK, Mi-Ri LEE, Bong-Seok JEON, Yong-Soo JOUNG, Sun-Hwan HWANG
  • Patent number: 10559569
    Abstract: A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Il-Sik Jang, Ji-Hwan Park, Mi-Ri Lee, Bong-Seok Jeon, Yong-Soo Joung, Sun-Hwan Hwang
  • Publication number: 20190244820
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 8, 2019
    Inventors: Tae-Su JANG, Jin-Chul PARK, Ji-Hwan PARK, Il-Sik JANG, Seong-Wan RYU, Se-In KWON, Jung-Ho SHIN, Dae-Jin HAM
  • Patent number: 10304684
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Tae-Su Jang, Jin-Chul Park, Ji-Hwan Park, Il-Sik Jang, Seong-Wan Ryu, Se-In Kwon, Jung-Ho Shin, Dae-Jin Ham
  • Publication number: 20180174845
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Application
    Filed: September 25, 2017
    Publication date: June 21, 2018
    Inventors: Tae-Su JANG, Jin-Chul PARK, Ji-Hwan PARK, Il-Sik JANG, Seong-Wan RYU, Se-In KWON, Jung-Ho SHIN, Dae-Jin HAM
  • Publication number: 20180175042
    Abstract: A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.
    Type: Application
    Filed: September 11, 2017
    Publication date: June 21, 2018
    Inventors: Il-Sik JANG, Ji-Hwan PARK, Mi-Ri LEE, Bong-Seok JEON, Yong-Soo JOUNG, Sun-Hwan HWANG
  • Patent number: 9570308
    Abstract: A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: February 14, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jae-Chun Cha, Seung-Woo Jin, An-Bae Lee, Il-Sik Jang
  • Publication number: 20160099152
    Abstract: A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.
    Type: Application
    Filed: December 14, 2015
    Publication date: April 7, 2016
    Inventors: Jae-Chun CHA, Seung-Woo JIN, An-Bae LEE, Il-Sik JANG
  • Patent number: 9245756
    Abstract: A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: January 26, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jae-Chun Cha, Seung-Woo Jin, An-Bae Lee, Il-Sik Jang
  • Publication number: 20150255291
    Abstract: A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.
    Type: Application
    Filed: August 12, 2014
    Publication date: September 10, 2015
    Inventors: Jae-Chun CHA, Seung-Woo JIN, An-Bae LEE, Il-Sik JANG
  • Publication number: 20120208333
    Abstract: A method for fabricating a semiconductor device includes: forming an impurity junction area within an area of the semiconductor substrate; forming a contact hole which partially exposes a surface the impurity junction area; and performing an additional ion implant process to implant impurity ions into the impurity junction area exposed through the contact hole, thereby increasing an impurity concentration of a surface portion of the impurity junction area.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 16, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: An Bae LEE, Seung Woo JIN, Yung Hwan JOO, Il Sik JANG, Jae Chun CHA