Abstract: A temperature compensation device for an optical communication device or the like is constructed so that an error value, which is the difference between the current temperature and a reference temperature, is subjected to digital processing in a temperature comparison unit. A digital error voltage value is calculated and digital PID control is performed instead of analog PID which requires electric components such as a power op-amp, a resistor (R), and a capacitor (C). According to this construction it is possible to reduce the number of electric parts. It is also possible to accept various types of temperature sensors while using only one PCB regardless of the types of temperature sensors utilized.

Abstract: Disclosed is a temperature controller and method for maintaining an optical-communication device at a constant temperature regardless of ambient temperature variation.

Abstract: Integrated circuit chips include an internal circuit including interconnected semiconductor devices that are configured to provide integrated circuit functionality, and a Test Element Group (TEG) circuit that is configured to allow measuring of electrical characteristics of the semiconductor devices. By providing a TEG circuit in the same integrated circuit chip as the internal circuit, the TEG circuit may accurately represent the electrical characteristics of the interconnected semiconductor devices of the internal circuit of the associated integrated circuit chip. The integrated circuit chip may be coupled to a test apparatus. The test apparatus includes a test probe that is configured to simultaneously contact the internal circuit and the TEG circuit. The test apparatus also can simultaneously test the integrated circuit functionality of the internal circuit, and measure the electrical characteristics of the semiconductor devices via the TEG circuit.

Abstract: A semiconductor memory device generates a test clock signal (whose periods and cycle number are variable) having a shorter cycle than that of an external clock signal, and internally test data using the test clock signal. The semiconductor memory device may repeatedly perform read/write operations using the internally generated test clock signal during a half cycle of the external clock signal. By comparing output data in the read operation with known data, a test apparatus may determine whether memory cells of a memory device are normal. In a low-frequency test apparatus, it is possible to screen disadvantages that may occur when a high-speed memory device operates at a high frequency.

Abstract: An array substrate of the present invention includes a storage capacitor that has a storage-on-gate structure. One embodiment of the present invention discloses the array substrate having a metal island pattern on the substrate beneath a drain electrode. The metal island pattern is disposed beneath a drain contact hole through which a pixel electrode contacts the drain electrode. Since the metal island pattern has the same thickness as the gate line, the passivation layer can have the same height both in a drain region and in a storage region. Over-etching is minimized with the passivation layer in the drain and storage region having the same uniform thickness.

Abstract: A method of fabricating liquid crystal display devices that includes plasma etching an insulation layer while simultaneously removing contaminates from the exposed surface of a substrate. Thinning of the substrate can then be performed by a subsequent etch process to form a highly planar substrate surface that can improve the picture quality of the completed LCD device.