Abstract: The present invention relates to a power supply and pickup system capable of maintaining stability of transmission efficiency despite changes in a resonant frequency. More particularly, the present invention relates to a power supply and pickup system capable of maintaining the stability of efficiency of transmitting power to a pickup device from a power supply device even when a voltage or current changes by the variation in a resonant frequency. According to the power supply and pickup system of the present invention, Q-factor of a power supply and pickup system is set to a low value, a stability of efficiency of transmitting power to a pickup device from a power supply device is maintained even when a voltage of current changes by the variation in a resonant frequency.

Abstract: The present invention relates to a power supply and pickup system capable of maintaining stability of transmission efficiency despite changes in a resonant frequency. More particularly, the present invention relates to a power supply and pickup system capable of maintaining the stability of efficiency of transmitting power to a pickup device from a power supply device even when a voltage or current changes by the variation in a resonant frequency. According to the power supply and pickup system of the present invention, Q-factor of a power supply and pickup system is set to a low value, a stability of efficiency of transmitting power to a pickup device from a power supply device is maintained even when a voltage of current changes by the variation in a resonant frequency.

Abstract: Provided us a visual cortical circuit apparatus comprising: a current mirror unit which uses a transistor as a current source to generate a current having the same size as that of a reaction; a transconductance unit which takes, as an input, the current generated by the current mirror unit and outputs a voltage using a transconductance; and a buffer unit for converting the voltage output from the transconductance unit into a current and buffering the current.

Abstract: Provided us a visual cortical circuit apparatus comprising: a current mirror unit which uses a transistor as a current source to generate a current having the same size as that of a reaction; a transconductance unit which takes, as an input, the current generated by the current mirror unit and outputs a voltage using a transconductance; and a buffer unit for converting the voltage output from the transconductance unit into a current and buffering the current.

Abstract: Provided us a visual cortical circuit apparatus comprising: a current mirror unit which uses a transistor as a current source to generate a current having the same size as that of a reaction; a transconductance unit which takes, as an input, the current generated by the current mirror unit and outputs a voltage using a transconductance; and a buffer unit for converting the voltage output from the transconductance unit into a current and buffering the current.

Abstract: Provided us a visual cortical circuit apparatus comprising: a current mirror unit which uses a transistor as a current source to generate a current having the same size as that of a reaction; a transconductance unit which takes, as an input, the current generated by the current mirror unit and outputs a voltage using a transconductance; and a buffer unit for converting the voltage output from the transconductance unit into a current and buffering the current.

Abstract: The present invention relates to a power supply and pickup system capable of maintaining stability of transmission efficiency despite changes in a resonant frequency. More particularly, the present invention relates to a power supply and pickup system capable of maintaining the stability of efficiency of transmitting power to a pickup device from a power supply device even when a voltage or current changes by the variation in a resonant frequency. According to the power supply and pickup system of the present invention, Q-factor of a power supply and pickup system is set to a low value, a stability of efficiency of transmitting power to a pickup device from a power supply device is maintained even when a voltage of current changes by the variation in a resonant frequency.

Abstract: There is provided a direct memory access apparatus and a direct memory access method. The direct memory access apparatus of the present invention comprises: a variable transmission rule map unit for setting a transmission rule with a variable block length and a variable block interval as a unit of memory transmission rule; a direct memory access unit for sending data line of the variable block length and the variable block interval, in case of access to the unit of memory by using the unit of memory transmission rule determined by the variable transmission rule map unit; and an interface unit for retrieving the unit of memory transmission rule, which is necessary for sending the data line of the variable block length and the variable block interval, from the variable transmission rule map unit and sending the unit of memory transmission rule to the direct memory access unit.

Abstract: Disclosed are a cache controller device, an interfacing method and a programming method using the same. The cache controller device prefetching and supplying data distributed in a memory to a main processor, includes: a cache temporarily storing data in a memory block having a limited size; a cache controller circularly reading out the data from the memory block to a cache memory, or transferring the data from the cache memory to the cache; and a memory input/output controller controlling prefetching the data to the cache, or transferring the data from the cache to a memory.

Abstract: There is provided a direct memory access apparatus and a direct memory access method. The direct memory access apparatus of the present invention comprises: a variable transmission rule map unit for setting a transmission rule with a variable block length and a variable block interval as a unit of memory transmission rule; a direct memory access unit for sending data line of the variable block length and the variable block interval, in case of access to the unit of memory by using the unit of memory transmission rule determined by the variable transmission rule map unit; and an interface unit for retrieving the unit of memory transmission rule, which is necessary for sending the data line of the variable block length and the variable block interval, from the variable transmission rule map unit and sending the unit of memory transmission rule to the direct memory access unit.

Abstract: A video signal is compressed by alternately removing predetermined arrangements of pixels, e.g. odd and even lines. In the case of an interlaced video signal, this may comprise removing the even fields of odd frames and odd fields of even frames. Two such compressed signals may be combined and transmitted in a channel having a bandwidth sufficient for one uncompressed signal only. In the case of non-interlaced video signals, odd and even lines, for example, may be removed from alternate frames. The removed lines can be replaced with odd and even lines taken from another video signal to produce a compressed video signal in which the lines are alternately from first and second uncompressed video signals.

Abstract: This invention relates to a high speed packet switching controller in a telephone switching system which can suitably be applied to a packet controller having large capacity using a neural network chip and maximize the system performance by the optimized switching operation. The high speed packet switching controller comprises a row address decoder for decoding a weight raw address which is inputted thereto, a column address decoder for decoding a weight column address which is inputted thereto, a matrix array for providing the neural network using address signals provided from the row address decoder and column address decoder and outputing varied voltage in accordance with an external weight value, a neural network for producing a final crossbar switching control signal, an external input/output bus for transmitting an output signal of the neural network, and an internal neural data bus for transmitting the address signal output from the row address decoder and column address decoder to the matrix array.

Abstract: Control-type continuous ramp converting apparatus and method therefore. The present invention provides real-time processing of neurons in the neural network, easy implementation and reduction of manufacture cost of high density neurons in the neural network.

Abstract: A multiplier and a neural network synapse capable of removing nonlinear current using current mirror circuits. The multiplier produces a linear current by using MOS transistors operating in a nonsaturation region. The multiplier includes a first current mirror including a plurality of MOS transistors to form a first current and a second current mirror including a plurality of MOS transistors to form a second current, wherein the second current mirror is coupled in parallel to the first current mirror. As a result, the multiplier outputs an output current by subtracting a second current from said first current.

Abstract: A multiplier capable of removing nonlinear current using current mirror circuits. The multiplier uses MOSFET and BJT devices by the BiCOMS processes. The multiplier includes three current mirror circuits. A first current mirror includes a BJT Q.sub.3 and a BJT Q.sub.5 and also the BJT Q.sub.3 is coupled in series to the n-channel MOSFET M1 between the voltage V.sub.1 and a ground voltage level. A second current mirror includes a BJT Q.sub.7 and a BJT Q.sub.8. A third current mirror includes a BJT Q.sub.4 and a BJT Q.sub.6. Consequently, input voltage signals V.sub.1 and V.sub.dc applied to the n-channel MOSFETs M1 determine the current I.sub.1 and input voltage signals V.sub.1 and V.sub.2 applied to the n-channel MOSFET M2 determine the current I.sub.2.