Abstract: A film mode detection method using a periodic pattern of a video sequence comprises the steps of: computing every absolute value of differences between every pair of corresponding pixels in two fields which are arranged within a predetermined distance on a time line; comparing a sum of the absolute value of differences between every corresponding pixels in two fields with the first predetermined threshold value M1 and limiting the sum to the first threshold value if the sum is greater than the first threshold value; filtering the video sequence and calculating a power of the filtered sum; and comparing the calculated power with the second predetermined threshold value M2 so as to determine the signal as a film mode if the power of the sum is greater than the second threshold value.

Abstract: A deinterlacing method based on an edge-directional interpolation in a conversion of video signals of an interlaced scanning format into those of a progressive scanning format, in which the unit of interpolation is extended from the unit of one pixel to the unit of one pixel group. An intermediate frame video is formed from an original interlaced field video. Mismatch values associated Keith edge directions are compared, thereby determining four edge directions exhibiting mismatch values less than those of other edge directions. An interpolation pixel value is calculated, using the intermediate video frame, indices of the four edge directions, and indices of the edge directions. A determination is made based on similarities of the four edge directions, differences among the less mismatch values associated with the four edge directions, and differences of the less mismatch values from mismatch values associated with the remaining edge directions.

Abstract: Disclosed is a motion-compensated interpolation (MCI)-based deinterlacing method for converting video signals of an interlaced scanning format into those of a progressive scanning format. The deinterlacing method involves a motion vector estimation step, a video signal deinterlacing step, a deinterlacing side-effect check step, and a deinterlaced result select step. The motion vector estimation step includes the steps of estimating a motion vector by the unit of a ½ pixel, using the previous frame, the current field, and the future field, and estimating a motion vector by the unit of a ¼ pixel, using the previous frame and the future field. Based oh a motion vector estimated at the motion vector estimation step, the video signal is deinterlaced.

Abstract: Disclosed are a deinterlacing method and apparatus based on a motion-compensated interpolation (MCI) and an edge-directional interpolation (EDI). The disclosed deinterlacing method and apparatus are characterized in that the deinterlacing of a video is conducted using both the MCI and EDI schemes in a single deinterlacing system. An input video signal of an interlaced scan format passes through an MCI block, an EDI block, and a line averaging interpolation (LAI) block, respectively. Respective resultant video signals outputted from the MCI and EDI blocks then pass through MCI and EDI side-effect checking blocks. Based on the checking results outputted from the side-effect checking blocks, a decision and combination block selects a desired one of the MCI, EDI, LAI pixel indices. The decision and combination block selects an output from the MCI block when MCI is superior whereas it selects an output from the EDI block when EDI is superior.

Abstract: A video decoding device for a TV receiver, e.g., SDTV, decodes a compressed video signal transmitted from a transmitting side and displays the decoded signal. The device includes a first downsampling part for downsampling input data in a unit of block at a predetermined ratio; a display size converting part for dividing the downsampled result into a first group of data and a second group of data and after downsampling the first group of data, for performing screen format conversion for the downsampled first group of data into a display size; a memory for storing each of the converted first group of data and the second group of data; and an output part for downsampling the second group of data to correspond with the first group of data to thereby perform screen format conversion for the downsampled second group of data, when the second group of data is reproduced, and for outputting the first and second groups of data.

Abstract: A digital signal processor being capable of rapidly operating a number of complex arithmetic formulae as such FFT. The digital signal processor operates data from first input line and data from second input line by a multiplier; operating data from any one of the first and second input lines and data from the first operating means by means of second operating means; and operating the data from any one of the first and second input lines and the data from the first operating means by means of third operating means. The data output from the multiplier is operates with any one from the first and second input lines by first accumulator. Also, the data output from the multiplier is operates with any one from the first and second input lines by second accumulator.

Abstract: The method and apparatus for eliminating noise in a video signal encoder according to the present invention divides an input video signal into a noise component and a pure video signal component and performs filtering gain control taking account of a rate of energy of the noise and pure signal, thereby performing the exact filtering with respect to an actual noise component and improving picture quality. The present invention also extracts a noise filtered signal component in advance, performs filtering of the remaining signal through gain control, and combines the extracted pure signal component and the filtered remaining signal, thereby eliminating the noise while keeping the resolution of the signal. If the video signal is processed in the unit of blocks, the noise filtering is performed considering this fact, thereby reducing blocking effect and improving picture quality.

Abstract: The present invention relates to an ISP server, a method of providing data, a method of advertising using moving pictures, and recording media therefor. In a method of providing data from the ISP server to an internet user's computer system connected through the internet, the method of advertising according to the present invention comprises the steps of (a) receiving a data reception speed of an internet user's internet connection, (b) selecting a data frame set based on the received data reception speed, and (c) transmitting the selected data frame set to the internet user's computer system. According to this method, a moving picture can be provided more efficiently during the process of receiving a prescribed service through the ISP server.

Abstract: A decoder for a digital TV receiver is disclosed. The present decoder improves the picture quality of a video signal down converted when an SD class TV receiver receives an HD class video signal. Generally, the decoder receives data in block units, converts a format of the data into a format for display, memorizes the data, processes the memorized data, and displays the processed data by converting the format to include more horizontal color signals than vertical color signals, memorizing and reproducing the data in downsampling the data in block units in a given ratio, and storing the data.

Abstract: A digital signal processor being capable of rapidly operating a number of complex arithmetic formulae as such FFT. The digital signal processor operates data from first input line and data from second input line by a multiplier; operating data from any one of the first and second input lines and data from the first operating means by means of second operating means; and operating the data from any one of the first and second input lines and the data from the first operating means by means of third operating means. The data output from the multiplier is operates with any one from the first and second input lines by first accumulator. Also, the data output from the multiplier is operates with any one from the first and second input lines by second accumulator.

Abstract: A digital signal processor being capable of rapidly operating a number of complex arithmetic formulae as such FFT. The digital signal processor operates data from first input line and data from second input line by a multiplier; operating data from any one of the first and second input lines and data from the first operating means by means of second operating means; and operating the data from any one of the first and second input lines and the data from the first operating means by means of third operating means. The data output from the multiplier is operates with any one from the first and second input lines by first accumulator. Also, the data output from the multiplier is operates with any one from the first and second input lines by second accumulator.

Abstract: An inverse discrete cosine transforming (IDCT) system for a digital television receiver performing a variable length decoding and an inverse quantization of an applied bit stream and an IDCT with respect to inversely quantized DCT coefficients, including an integrated IDCT part which performs an inverse discrete cosine transformation of standards DCT coefficients inversely quantized or high definition DCT coefficients inversely quantized.

Abstract: A film mode detection method using a periodic pattern of a video sequence comprises the steps of: computing every absolute value of differences between every pair of corresponding pixels in two fields which are arranged within a predetermined distance on a time line; comparing a sum of the absolute value of differences between every corresponding pixels in two fields with the first predetermined threshold value M1 and limiting the sum to the first threshold value if the sum is greater than the first threshold value; filtering the video sequence and calculating a power of the filtered sum; and comparing the calculated power with the second predetermined threshold value M2 so as to determine the signal as a film mode if the power of the sum is greater than the second threshold value.

Abstract: A digital signal processor having an ALU and accumulating register small in bit number. The digital signal processor adds r-bit rounding bits to an N-bit data(wherein r<N) and adds g-bit guard bits to the high-order bits of the data using bit alignment units each being implemented with a wiring, when N bit data is processed. The data added by the guard bits and the rounding bits is operated by means of the accumulator. The operated data is selectively rounded by a rounding processor. Also, the selectively rounded data is selectively saturated by a saturation processor.

Abstract: An improved decision-feedback equalizer for a digital communication system, which is capable of preventing performance degradation which occurs due to a pipelining delay, includes a feed forward filter, a subtractor, a slicer, first and second feedback filters, and an adder. The feed forward filter filters out a precursor ISI signal from a digital signal. The subtractor subtracts a summation ISI signal from the digital signal output by the feed forward filter, and the slicer slices the output of the subtractor into symbols having a predetermined size. The first feedback filter has a predetermined number of pipelining delays, and filters the output from the slicer to generate a first post-cursor ISI signal. The second feedback filter also filters the output of the slicer to generate a second post-cursor ISI signal within the predetermined pipelining delay number of the first feedback filter without a pipelining delay.