Patents by Inventor Il Ung Kim

Il Ung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5940680
    Abstract: A method for manufacturing a known good die array("KGD" array ), which includes the steps of: (a) forming a plurality of circuit patterns, and bonding pads to match solder bumps on a wafer; (b) providing solder bumps on the bonding pads; (c) forming metal layers for wire-bonding on the solder bumps; (d) dividing the wafer having metal layers into respective individual circuit pattern unit dies; (e) holding at least one die in a die holder for testing; (f) wire-bonding circuit contacts of the die holder with the metal layers using wires; (g) testing the die which is electrically interconnected with the die holder; and (h) removing simultaneously the metal layer on the solder bumps for wire bonding and the wires from the die to give a known good die array having solder bumps.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: August 17, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu Jin Lee, Sang Hyeog Lee, In Ho Hyun, Il Ung Kim
  • Patent number: 5644247
    Abstract: A test socket and a method for identifying a known good die using the test socket. The test socket includes a substrate having penetrating apertures, and land patterns formed around the penetrating apertures. The substrate has contact terminals at one side which are connected to the outside, and a protective casing is installed on the upper part of the substrate. After the semiconductor chips are mounted in the test socket by a piece of adhesive tape, to cover the penetrating apertures of the substrate, the bonding pads of the semiconductor chips and the land patterns of the substrate are connected to each other by wires. The test socket is then installed on a burn-in test board to carry out a burn-in test. The wires of the bare chips, which have been subjected to the burn-in test are cut by a cutting device, and a lower portion of each semiconductor chip corresponding to a known good die, is hit by an ejection pin through the penetrating apertures of the substrate to separate and obtain the known good dies.
    Type: Grant
    Filed: May 9, 1996
    Date of Patent: July 1, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In Ho Hyun, Sang Hyeong Lee, Il Ung Kim
  • Patent number: 5479105
    Abstract: A die testing apparatus according to the present invention includes a lead frame having a plurality of die pads, wherein a plurality of bare chips are mounted on the die pads. The bonding pads of each bare chips are connected to a plurality of leads associated with each die pad through a plurality of bonding wires. The die pads are supported by a plurality of tie bars and the leads are supported by an adhesion tape attached to the lead frame. The lead frame is placed in a test socket which includes an under socket having a plurality of slot grooves and an upper socket hinged with the under socket and having a plurality of slot holes and a plurality of test probes contacting the leads of the lead frame.
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: December 26, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il Ung Kim, Si Don Choi