Abstract: An eyelash curler composed of a main body, having an upper body part; a lower body part having a curved forming space at a front section thereof, to allow eyelashes of the user to be positioned therein, the lower body part constituting a handle grip body with the upper body part; an immobilizing member provided at a front end of the lower body part and curved to correspond to curvature of an eyelash line shape; a forming member coupled to the immobilizing member and made of a metal sheet having the same curvature as that of the immobilizing member; and a pressing member disposed between the upper and lower body parts, which includes a pressing plate; a pressing part integrally connected to a front end of the pressing plate through a boundary part; and an elastically pressing part coupled to a front end of the pressing part.

Abstract: Provided is a data bus system for a micro controller which has an input/output (I/O) unit, a central processing unit (CPU), an internal memory unit, and a peripheral circuitry. The data bus system includes an external access bus used when data is output from the CPU or data is input to the I/O unit or the internal memory unit; an internal access bus used when data is input to the CPU, data is output from the I/O unit or the internal memory unit, or data is input to or output from the peripheral circuitry; and an internal memory test bus used when data is output from the internal memory unit and input to the I/O unit.

Abstract: The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.

Abstract: Disclosed is a filing tool for hardened-skin care, including a plurality of filing parts having double plated nickel and stone powders fixed to such nickel on a metal plate. A method of manufacturing the filing tool is also provided, including setting a patterned photosensitive dry film on the metal plate, exposing the metal plate set with the dry film to light, removing a non-exposed portion of the dry film to form a masking pattern, plating nickel on the metal plate formed with the masking pattern to form a first nickel-plated layer, followed by uniformly applying stone powders on the first nickel-plated layer, further plating nickel on the stone powders to form a second nickel-plated layer, and fixing the stone powders between the first nickel-plated layer and the second nickel-plated layer, followed by removing the masking pattern. Thereby, since the stone powders, serving as a filing material, are securely fixed to nickel, filing efficiencies improve.

Abstract: An eyelash curler is composed of an eyelash curler main body, which includes an upper body part; a lower body part having a curved forming space at a front section thereof, to allow eyelashes of the user to be positioned therein, the lower body part constituting a handle grip body together with the upper body part; an immobilizing member provided at a front end of the lower body part and curved to correspond to curvature of an eyelash line shape of a user; a forming member coupled to the immobilizing member and made of a metal sheet having the same curvature as that of the immobilizing member; and a pressing member disposed between the upper and lower body parts, which includes a pressing plate, which is rotatably supported to the curler main body by a pin formed on a rear end thereof, and which is biased by an elastic element; a pressing part integrally connected to a front end of the pressing plate through a boundary part; and an elastically pressing part coupled to a front end of the pressing part.

Abstract: The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate.

Abstract: A method for fabricating a power semiconductor device having a trench gate structure is provided. An epitaxial layer of a first conductivity type having a low concentration and a body region of a second conductivity type are sequentially formed on a semiconductor substrate of the first conductivity type having a high concentration. An oxide layer pattern is formed on the body region. A first trench is formed using the oxide layer pattern as an etching mask to perforate a predetermined portion of the body region having a first thickness. A body contact region of the second conductivity type having a high concentration is formed to surround the first trench by impurity ion implantation using the oxide layer pattern as an ion implantation mask. First spacer layers are formed to cover the sidewalls of the first trench and the sidewalls of the oxide layer pattern.

Abstract: Disclosed is a low power and high density source driver and a current driven active matrix organic electroluminescent device having the same, in which all elements operate at a normal voltage and all circuits of the source driver are shielded from a high voltage of a panel.

Abstract: The MOS transistor of the present invention is manufactured by a conventional complementary MOS transistor technology. In the manufacturing method of the MOS transistor having nanometer dimensions, a gate having dimensions at a nanometer scale can be formed through control of the width of spacers instead of with a specific lithography technology. The doped spacers are used for forming source/drain extension regions having an ultra-shallow junction, thereby avoiding damage on the substrate caused by ion implantation. In addition, a dopant is diffused from the doped space into a semiconductor substrate through annealing to form the source/drain extension regions having an ultra-shallow junction.

Abstract: Provided is a data bus system for a micro controller which has an input/output (I/O) unit, a central processing unit (CPU), an internal memory unit, and a peripheral circuitry. The data bus system includes an external access bus used when data is output from the CPU or data is input to the I/O unit or the internal memory unit; an internal access bus used when data is input to the CPU, data is output from the I/O unit or the internal memory unit, or data is input to or output from the peripheral circuitry; and an internal memory test bus used when data is output from the internal memory unit and input to the I/O unit.

Abstract: The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit.

Abstract: The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.

Abstract: The MOS transistor of the present invention is manufactured by a conventional complementary MOS transistor technology. In the manufacturing method of the MOS transistor having nanometer dimensions, a gate having dimensions at a nanometer scale can be formed through control of the width of spacers instead of with a specific lithography technology. The doped spacers are used for forming source/drain extension regions having an ultra-shallow junction, thereby avoiding damage on the substrate caused by ion implantation. In addition, a dopant is diffused from the doped space into a semiconductor substrate through annealing to form the source/drain extension regions having an ultra-shallow junction.

Abstract: The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit.

Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.