Abstract: A semiconductor device includes a stack structure including conductive layers and insulating layers, which are alternately stacked; an opening including a first opening penetrating the stack structure and second openings protruding from the first opening; and a channel layer including channel regions located in the second openings and impurity regions located in the first opening, the impurity regions having an impurity concentration higher than that of the channel regions.

Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.

Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Abstract: A semiconductor device includes a stack structure including conductive layers and insulating layers, which are alternately stacked; an opening including a first opening penetrating the stack structure and second openings protruding from the first opening; and a channel layer including channel regions located in the second openings and impurity regions located in the first opening, the impurity regions having an impurity concentration higher than that of the channel regions.

Abstract: A method for fabricating the three dimensional (3D), non-volatile memory (NVM) device includes: forming a stacked structure including a plurality of interlayer insulating layers and a plurality of first material layers which are alternately stacked; forming at least one channel hole penetrating through the stack structure; forming a second material layer along the at least one channel hole; trimming a surface of the second material layer; oxidizing a whole of the trimmed second material layer to form at least a portion of a charge blocking layer; and forming a charge storage layer and a tunnel insulating layer over the charge blocking layer.

Abstract: A semiconductor device includes a stack structure including conductive layers and insulating layers, which are alternately stacked; an opening including a first opening penetrating the stack structure and second openings protruding from the first opening; and a channel layer including channel regions located in the second openings and impurity regions located in the first opening, the impurity regions having an impurity concentration higher than that of the channel regions.

Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Abstract: A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line.

Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Abstract: A semiconductor memory device includes a first dummy transistor coupled to a bit line, a first select transistor formed where a first selection line surrounds a vertical channel layer, a second dummy transistor coupled to a common source line, a second select transistor formed where a second selection line surrounds the vertical channel layer, and main cell transistors coupled between the first and second select transistors.

Abstract: A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line.

Abstract: A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line.

Abstract: A semiconductor memory device includes a first dummy transistor coupled to a bit line, a first select transistor formed where a first selection line surrounds a vertical channel layer, a second dummy transistor coupled to a common source line, a second select transistor formed where a second selection line surrounds the vertical channel layer, and main cell transistors coupled between the first and second select transistors.

Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Abstract: A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line.

Abstract: In an erase method of a flash device, including a page buffer configured to transfer a virtual voltage in response to a discharge signal and further comprising strings each including memory cells and coupled to the page buffer via a respective bit line, applying a ground voltage to a gate of each of the memory cells and erasing the memory cells coupled to a selected bit line by supplying the virtual voltage wherein the virtual voltage is applied to the selected bit line and a unselected bit line.

Abstract: In an erase method of a flash device, including a page buffer configured to transfer a virtual voltage in response to a discharge signal and further comprising strings each including memory cells and coupled to the page buffer via a respective bit line, applying a ground voltage to a gate of each of the memory cells and erasing the memory cells coupled to a selected bit line by supplying the virtual voltage wherein the virtual voltage is applied to the selected bit line and a unselected bit line.