Abstract: A method for error correction, the method comprises receiving a codeword that comprises a payload and a redundancy section; error-correction decoding the codeword by applying a syndrome-based error correction process to provide an amended payload and an error-correction decoding success indicator; wherein the amended payload comprises an amended CRC signature and an amended payload data; calculating, using the amended payload CRC signature, a validity of the amended payload to provide a CRC validity result; estimating a number of errors in the redundancy section; and determining that the error-correction succeeded when the number of errors in the redundancy section did not exceed a threshold, the error correction success indicator indicates that the error-correction decoding failed, and the CRC validity result indicates that the amended payload is valid.

Abstract: A method comprising: generating or receiving read threshold information indicative of multiple read thresholds values that were applied when reading multiple flash memory cells that belong to multiple rows of a flash memory module; and generating a compressed representation of reference read thresholds to be applied during future read operations of the flash memory cells in response to the read threshold information.

Abstract: A method of managing a non-volatile memory module, the method may include: receiving data sectors during a set of at least one write transactions; selecting, out of the currently buffered portions, to-be-merged memory space portions and to-be-cleaned memory space portions; merging, for each to-be-merged memory space portion and before the buffer becomes full, data sectors that belong to the to-be-merged memory space portion into a sequential portion of the non-volatile memory module, wherein the sequential portion differs from the buffer; and copying, for each to-be-cleaned memory space and before the buffer becomes full, data sectors that belong to the to-be-cleaned memory space portion into a buffer block of the buffer.

Abstract: A system and method for unbiased rounding away from, or toward, zero by truncating N bits from a M bit input number to provide a M?N bit number, and adding the equivalent value of ‘½’ to the M?N bit number unless the input number is negative, or positive, respectively, and the N truncated bits represent exactly ½. The method for rounding away from zero may include outputting a (M?N) bit truncated number if the M-bit input number is negative and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros; and otherwise, computing and outputting a sum of (a) a number that has an equivalent value of one followed by (N?1) replicas of zero, the one provided by applying a logical operation on the most significant bit of the sequence of truncated bits and (b) the (M?N) bit truncated number.

Abstract: A flash memory controller, a non-transitory computer readable medium and a method for reading flash memory cells of a flash memory module. The method may include calculating a group of read thresholds to be applied during a reading operation of a set of flash memory cells that belong to a certain row of the flash memory module based upon a compressed representation of reference read thresholds associated with multiple reference rows of the flash memory module; and reading the set of flash memory cells by applying the group of reference read thresholds to provide read results.

Abstract: A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.

Abstract: A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.

Abstract: A system and method for decoding multi-dimensional encoded data. A set of multi-dimensional encoded data may be received encoding each input bit in a set of input bits by multiple different component codes in multiple different encoding dimensions. The multi-dimensional data may potentially have errors. A map may be used to locate each set of intersection bits that encode the same input bit by multiple unsolved component codes. The unsolved component codes may be decoded using one or a plurality of tested error correction hypotheses that yields a decoding success, where each hypothesis correcting a different set of intersection bits for a different input bit. The successful hypothesis may be applied for correcting the multi-dimensional encoded data.

Abstract: A system and method is provided for decoding a set of bits using a plurality of hypotheses, for example, each independently tested on-the-fly. Initial bit states and associated reliability metrics may be received for the set of bits. A current hypothesis may be decoded for correcting the set of bits, wherein the current hypothesis defines different bit states and associated reliability metrics for the set of bits. If decoding the current hypothesis is not successful, a subsequently ordered hypothesis may be decoded, wherein the hypotheses are ordered such that their associated reliability metric is a monotonically non-decreasing sequence. Decoding may proceed iteratively until the current hypothesis is successful.

Abstract: A method and system for writing in flash memory, the system operative for, and the method comprising, writing data onto a plurality of logical pages characterized by a plurality of different probabilities of error respectively, the writing including encoding data intended for each of the plurality of physical pages using a redundancy code with a different code rate for each individual physical page, the code rate corresponding to the probability of error in the individual logical page.

Abstract: A system and method is provided for decoding a set of bits using a plurality of hypotheses, for example, each independently tested on-the-fly. Initial bit states and associated reliability metrics may be received for the set of bits. A current hypothesis may be decoded for correcting the set of bits, wherein the current hypothesis defines different bit states and associated reliability metrics for the set of bits. If decoding the current hypothesis is not successful, a subsequently ordered hypothesis may be decoded, wherein the hypotheses are ordered such that their associated reliability metric is a monotonically non-decreasing sequence. Decoding may proceed iteratively until the current hypothesis is successful.

Abstract: A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.

Abstract: A system and method for decoding multi-dimensional encoded data. A set of multi-dimensional encoded data may be received encoding each input bit in a set of input bits by multiple different component codes in multiple different encoding dimensions. The multi-dimensional data may potentially have errors. A map may be used to locate each set of intersection bits that encode the same input bit by multiple unsolved component codes. The unsolved component codes may be decoded using one or a plurality of tested error correction hypotheses that yields a decoding success, where each hypothesis correcting a different set of intersection bits for a different input bit. The successful hypothesis may be applied for correcting the multi-dimensional encoded data.

Abstract: System and method for storing data in a non-volatile memory including a multi-level cell and single-level cell memory portions. To write a dataset to the non-volatile memory, if the size of the dataset is equal to the size of pages in the multi-level cell memory portion, the dataset may be written directly to the multi-level cell memory portion to fill an integer number of pages in a single write operation. However, if the size of the dataset is different than the size of the multi-level cell memory pages, at least a portion of the dataset may be temporarily written to the single-level cell memory portion until data is accumulated in a plurality of write operations having a size equal the size of the multi-level cell memory pages. The accumulated data may fill an integer number of the pages in the multi-level cell memory portion in a single write operation.

Abstract: A system and method for unbiased rounding away from, or toward, zero comprising apparatus for truncating N bits from an original M bit input number thereby to provide a M?N bit number, and apparatus for adding the equivalent value of ‘½’ to the M?N bit number unless the input number is negative, or positive, respectively, and the N truncated bits represent exactly ½.

Abstract: A method and system for writing in flash memory, the system operative for, and the method comprising, writing data onto a plurality of logical pages characterized by a plurality of different probabilities of error respectively, the writing including encoding data intended for each of the plurality of physical pages using a redundancy code with a different code rate for each individual physical page, the code rate corresponding to the probability of error in the individual logical page.