Patents by Inventor Ilan Ben-Yaacov
Ilan Ben-Yaacov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220183900Abstract: A compression device for applying pressure to a body part can include a fabric member that can fit over the body part, and one or more actuators coupled to the fabric member, wherein each of the one or more actuators is configured to cause at least a portion of the fabric member to expand or contract along a circumferential direction, thereby decreasing or increasing the pressure applied to the body part adjacent to the actuator. The fabric member can be thin and stretchable, and can contour the body part over which it is worn. The actuators can cause user controlled variable pressure levels to be applied to the body part, including constant pressure levels as well as time varying synchronous or asynchronous pressure patterns.Type: ApplicationFiled: March 8, 2022Publication date: June 16, 2022Inventor: Ilan Ben-Yaacov
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Patent number: 9941399Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: GrantFiled: August 19, 2016Date of Patent: April 10, 2018Assignee: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 9935190Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.Type: GrantFiled: March 9, 2016Date of Patent: April 3, 2018Assignee: Transphorm Inc.Inventors: Mo Wu, Rakesh K. Lal, Ilan Ben-Yaacov, Umesh Mishra, Carl Joseph Neufeld
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Patent number: 9634100Abstract: Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.Type: GrantFiled: November 6, 2015Date of Patent: April 25, 2017Assignee: Transphorm Inc.Inventors: Umesh Mishra, Srabanti Chowdhury, Ilan Ben-Yaacov
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Patent number: 9590088Abstract: A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.Type: GrantFiled: December 10, 2014Date of Patent: March 7, 2017Assignee: The Regents of the University of CaliforniaInventors: Srabanti Chowdhury, Ramya Yeluri, Christophe Hurni, Umesh K. Mishra, Ilan Ben-Yaacov
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Publication number: 20160359030Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: ApplicationFiled: August 19, 2016Publication date: December 8, 2016Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 9437708Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: GrantFiled: November 18, 2015Date of Patent: September 6, 2016Assignee: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 9432210Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining a current location and receiving energy usage information from devices in the location.Type: GrantFiled: June 17, 2013Date of Patent: August 30, 2016Assignee: Zuli, Inc.Inventors: Siddhant Bhargava, Taylor Keith Umphreys, Benjamin Jerming Chang, Paul Morgan Pattison, Ilan Ben-Yaacov
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Publication number: 20160190298Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.Type: ApplicationFiled: March 9, 2016Publication date: June 30, 2016Inventors: Mo Wu, Rakesh K. Lal, Ilan Ben-Yaacov, Umesh Mishra, Carl Joseph Neufeld
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Patent number: 9318593Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.Type: GrantFiled: November 17, 2014Date of Patent: April 19, 2016Assignee: Transphorm Inc.Inventors: Mo Wu, Rakesh K. Lal, Ilan Ben-Yaacov, Umesh Mishra, Carl Joseph Neufeld
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Publication number: 20160071951Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: ApplicationFiled: November 18, 2015Publication date: March 10, 2016Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Publication number: 20160064495Abstract: Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.Type: ApplicationFiled: November 6, 2015Publication date: March 3, 2016Inventors: Umesh Mishra, Srabanti Chowdhury, Ilan Ben-Yaacov
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Publication number: 20160020313Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.Type: ApplicationFiled: November 17, 2014Publication date: January 21, 2016Inventors: Mo Wu, Rakesh K. Lal, Ilan Ben-Yaacov, Umesh Mishra, Carl Joseph Neufeld
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Patent number: 9196716Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: GrantFiled: August 20, 2014Date of Patent: November 24, 2015Assignee: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 9184275Abstract: Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.Type: GrantFiled: June 27, 2012Date of Patent: November 10, 2015Assignee: Transphorm Inc.Inventors: Umesh Mishra, Srabanti Chowdhury, Ilan Ben-Yaacov
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Patent number: 9041065Abstract: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.Type: GrantFiled: August 22, 2013Date of Patent: May 26, 2015Assignee: Transphorm Inc.Inventors: Yifeng Wu, Umesh Mishra, Primit Parikh, Rongming Chu, Ilan Ben-Yaacov, Likun Shen
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Publication number: 20150137137Abstract: A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.Type: ApplicationFiled: December 10, 2014Publication date: May 21, 2015Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Srabanti Chowdhury, Ramya Yeluri, Christophe Hurni, Umesh K. Mishra, Ilan Ben-Yaacov
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Patent number: 8937338Abstract: A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.Type: GrantFiled: June 20, 2012Date of Patent: January 20, 2015Assignee: The Regents of the University of CaliforniaInventors: Srabanti Chowdhury, Ramya Yeluri, Christophe Hurni, Umesh K. Mishra, Ilan Ben-Yaacov
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Publication number: 20140361309Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: ApplicationFiled: August 20, 2014Publication date: December 11, 2014Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 8841702Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: GrantFiled: July 30, 2013Date of Patent: September 23, 2014Assignee: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh