Patents by Inventor Ilan Bloom
Ilan Bloom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9910729Abstract: A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array.Type: GrantFiled: July 14, 2015Date of Patent: March 6, 2018Assignee: Cypress Semiconductor CorporationInventors: Ilan Bloom, Amichai Givant, Yoav Yogev, Amit Shefi
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Patent number: 9543017Abstract: A memory chip includes a memory array and a two-dimensional sensing system. The array includes a multiplicity of memory cells connected in rows by word lines and in columns by bit lines. The sensing system moves a read point two-dimensionally within a two-dimensional read space as the two-dimensional read space shrinks and shifts over the life of the chip.Type: GrantFiled: March 18, 2012Date of Patent: January 10, 2017Assignee: Cypress Semiconductors Ltd.Inventors: Ilan Bloom, Alexander Kushnarenko
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Patent number: 9490261Abstract: A nitride read only memory (NROM) array includes a silicon substrate having trenches therein, a plurality of polysilicon bit lines deposited in the trenches and connecting columns of memory cells, a layer of (oxide nitride oxide) ONO at least within the memory cells and a plurality of polysilicon word lines to connect rows of the memory cells. An NROM array with a virtual ground architecture includes a plurality of bit lines to connect columns of NROM memory cells, a layer of ONO at least within the memory cells and a plurality of word lines to connect rows of the NROM memory cells, wherein a distance between word lines is at least twice the width of the word lines.Type: GrantFiled: October 19, 2011Date of Patent: November 8, 2016Assignee: Cypress Semiconductor Ltd.Inventors: Ilan Bloom, Amichai Givant, Boaz Eitan
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Patent number: 9081710Abstract: A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array.Type: GrantFiled: April 11, 2013Date of Patent: July 14, 2015Assignee: Spansion LLC.Inventors: Ilan Bloom, Amichai Givant, Yoav Yogev, Amit Shefi
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Publication number: 20140310569Abstract: A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array.Type: ApplicationFiled: April 11, 2013Publication date: October 16, 2014Inventors: Ilan BLOOM, Amichai GIVANT, Yoav YOGEV, Amit SHEFI
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Publication number: 20140233339Abstract: A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line.Type: ApplicationFiled: February 18, 2013Publication date: August 21, 2014Applicant: SPANSION LLC.Inventors: Amichai GIVANT, Ilan BLOOM, Mark RANDOLPH, Zhizheng LIU
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Publication number: 20130242669Abstract: A memory chip includes a memory array and a two-dimensional sensing system. The array includes a multiplicity of memory cells connected in rows by word lines and in columns by bit lines. The sensing system moves a read point two-dimensionally within a two-dimensional read space as the two-dimensional read space shrinks and shifts over the life of the chip.Type: ApplicationFiled: March 18, 2012Publication date: September 19, 2013Applicant: SPANSION ISRAEL LTDInventors: Ilan BLOOM, Alexander KUSHNARENKO
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Patent number: 8264884Abstract: The present invention includes methods, circuits and systems for reading non-volatile memory (“NVM”) cells, including multi-level NVM cells. According to some embodiments of the present invention, there may be provided a NVM cell threshold voltage detection circuit adapted to detect an approximate threshold voltage associated with a charge storage region of a NVM cell, where the NVM cell may be a single or a multi-charge storage region cell. A decoder circuit may be adapted to decode and/or indicate the logical state of a NVM cell charge storage region by mapping or converting a detected approximate threshold voltage of the charge storage region into a logical state value.Type: GrantFiled: September 16, 2007Date of Patent: September 11, 2012Assignee: Spansion Israel LtdInventors: Ilan Bloom, Eduardo Maayan
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Publication number: 20120098052Abstract: A nitride read only memory (NROM) array includes a silicon substrate having trenches therein, a plurality of polysilicon bit lines deposited in the trenches and connecting columns of memory cells, a layer of (oxide nitride oxide) ONO at least within the memory cells and a plurality of polysilicon word lines to connect rows of the memory cells. An NROM array with a virtual ground architecture includes a plurality of bit lines to connect columns of NROM memory cells, a layer of ONO at least within the memory cells and a plurality of word lines to connect rows of the NROM memory cells, wherein a distance between word lines is at least twice the width of the word lines.Type: ApplicationFiled: October 19, 2011Publication date: April 26, 2012Inventors: Ilan Bloom, Amichai Givant, Boaz Eitan
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Patent number: 7804126Abstract: A non-volatile memory array has word lines spaced a sub-F (sub-minimum feature size F) width apart and bit lines generally perpendicular to the word lines. The present invention also includes a method for word-line patterning of a non-volatile memory array which includes generating sub-F word lines from mask generated elements with widths of at least a minimum feature size F.Type: GrantFiled: July 18, 2006Date of Patent: September 28, 2010Assignee: Saifun Semiconductors Ltd.Inventors: Boaz Eitan, Ilan Bloom, Rustom Irani
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Patent number: 7786512Abstract: A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and bit lines generally perpendicular to the word lines, with a word line pitch of less than 2 F. In one embodiment, the word lines are made of polysilicon spacers.Type: GrantFiled: July 18, 2006Date of Patent: August 31, 2010Assignee: Saifun Semiconductors Ltd.Inventors: Ilan Bloom, Boaz Eitan, Rustom Irani
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Patent number: 7652930Abstract: The present invention is a method circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array. One or more NVM cells of a memory array may be erased using an erase pulse produced by a controller and/or erase pulse source adapted to induce and/or invoke a substantially stable channel current in the one or more NVM cells during an erasure procedure. The voltage profile of an erase pulse may be predefined or the voltage profile of the erase pulse may be dynamically adjusted based on feedback from a current sensor during an erase procedure.Type: GrantFiled: April 3, 2005Date of Patent: January 26, 2010Assignee: Saifun Semiconductors Ltd.Inventors: Assaf Shappir, Ilan Bloom, Boaz Eitan
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Publication number: 20090323423Abstract: The present invention includes methods, circuits and systems for reading non-volatile memory (“NVM”) cells, including multi-level NVM cells. According to some embodiments of the present invention, there may be provided a NVM cell threshold voltage detection circuit adapted to detect an approximate threshold voltage associated with a charge storage region of a NVM cell, where the NVM cell may be a single or a multi-charge storage region cell. A decoder circuit may be adapted to decode and/or indicate the logical state of a NVM cell charge storage region by mapping or converting a detected approximate threshold voltage of the charge storage region into a logical state value.Type: ApplicationFiled: September 16, 2007Publication date: December 31, 2009Inventors: Ilan Bloom, Eduardo Maayan
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Patent number: 7638835Abstract: An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.Type: GrantFiled: December 28, 2006Date of Patent: December 29, 2009Assignee: Saifun Semiconductors Ltd.Inventors: Rustom Irani, Boaz Eitan, Ilan Bloom, Assaf Shappir
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Publication number: 20090129166Abstract: Disclosed is a method, circuit and system for evaluating the status of a data storage area in a non-volatile memory cell within a non-volatile memory cell array. According to some embodiments of the present invention, leakage current in at least one other cell in proximity with the cell being evaluated is suppressed. Leakage current suppression may be achieved by applying a suppression voltage to the word of the cell(s) whose leakage current(s) are to be suppressed.Type: ApplicationFiled: November 15, 2007Publication date: May 21, 2009Inventors: Eduardo Maayan, Ilan Bloom
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Publication number: 20080239599Abstract: A clamping scheme using dual sensing detection, which can sense and differentiate (in the extreme) between a high voltage level and fast (enough) slope (indicative of ESD), and low voltage level and slow slope (indicative of normal operation) and/or low voltage level and fast slope (indicative of hot insertion). It can also generate a locking scheme to ensure proper discharging only if the level is above high level and fast slope. It can also operate the clamping for a short time only if the level is below the high level but above the low level, and of sufficient slope.Type: ApplicationFiled: April 1, 2007Publication date: October 2, 2008Inventors: Yehuda Yizraeli, Yoram Betser, Ilan Bloom
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Patent number: 7317633Abstract: A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor and an NMOS transistor the PMOS transistors sharing a common deep N well and the NMOS transistors connected to a P well, wherein during negative charging, the NMOS transistors shunt leakage current to ground, and during positive charging, the PMOS transistors shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.Type: GrantFiled: July 5, 2005Date of Patent: January 8, 2008Assignee: Saifun Semiconductors LtdInventors: Eli Lusky, Ilan Bloom, Assaf Shappir, Boaz Eitan
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Publication number: 20070200180Abstract: An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.Type: ApplicationFiled: December 28, 2006Publication date: August 30, 2007Inventors: Rustom Irani, Boaz Eitan, Ilan Bloom, Assaf Shappir
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Publication number: 20070141788Abstract: A method for embedding NROM process steps and HV CMOS devices into high-speed logic CMOS process steps, the method including forming isolation areas for NROM and high voltage CMOS elements, forming high thermal drive process elements of the NROM and the HV CMOS elements, forming mid thermal drive process elements of the logic CMOS elements, and forming low thermal drive process elements for the logic CMOS and for the NROM and the high voltage CMOS elements.Type: ApplicationFiled: November 27, 2006Publication date: June 21, 2007Inventors: Ilan Bloom, Eli Lusky
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Publication number: 20070051982Abstract: A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and bit lines generally perpendicular to the word lines, with a word line pitch of less than 2 F. In one embodiment, the word lines are made of polysilicon spacers.Type: ApplicationFiled: July 18, 2006Publication date: March 8, 2007Applicant: Saifun Semiconductors Ltd.Inventors: Ilan Bloom, Boaz Eitan, Rustom Irani