Abstract: A self-correcting memory system comprising an integrated circuit including memory and memory content authentication functionality, which is operative to compare content to be authenticated to a standard and to output “authentic” if the content to be authenticated equals the standard and “non-authentic” otherwise; and error correction functionality which is operative to apply at least one possible correction to at least one erroneous word entity in said memory, yielding a possibly correct word entity, call said authentication for application to the possibly correct word entity, and if the authentication's output is “authentic”, to replace said erroneous word entity in said memory, with said possibly correct word entity thereby to yield error correction at a level of confidence derived from the level of confidence associated with the authentication.

Abstract: A system for verifying integrity of content of an integrated circuit's registers, the system being operative in conjunction with an integrated circuit including at least one memory, at least one processor, and a multiplicity of registers, the system comprising register content verification logic configured, when in a first mode aka “Study Mode”, to read at least some of the registers' content, to compute a first hash on the content, and to store the first hash thereby to provide an up-to-date reference hash, and, at least on occasion, when in a second mode aka “Verify Mode”, to compute at least one second hash on the content, to compare the second hash to the reference hash and, accordingly, to provide a content verification output (aka “fault detection” output) indicative of whether the reference and second hashes are equal.

Abstract: System, method and computer program product for prioritizing trial-and-error attempted corrections of bit/s, in a memory, in which logical bit levels are determined by thresholding voltage values using threshold/s, the method comprising ranking bits such that a first bit is ranked before a second bit, which is less likely than said first bit to be erroneous and sequentially attempting to correct the bits in order of the ranking, including attempting to correct the first bit before attempting to correct the second bit.

Abstract: A chip aka integrated circuit, the chip comprising configuration register/s, typically volatile, and/or at least one on-chip non-volatile memory m typically including at least one reserved memory location, which may be reserved for storing contents of at least one typically volatile configuration register r, from among the configuration registers; and/or apparatus configured for, at least once, storing values which may be indicative of content of at least one typically volatile configuration register r from among the registers, e.g. in the on-chip non-volatile memory m, e.g. at the at least one reserved memory location.

Abstract: A chip aka integrated circuit, the chip comprising configuration register/s, typically volatile, and/or at least one on-chip non-volatile memory m typically including at least one reserved memory location, which may be reserved for storing contents of at least one typically volatile configuration register r, from among the configuration registers; and/or apparatus configured for, at least once, storing values which may be indicative of content of at least one typically volatile configuration register r from among the registers, e.g. in the on-chip non-volatile memory m, e.g. at the at least one reserved memory location.

Abstract: A security system configured for deployment on a chip which is to be protected, the system comprising fault injection detection subsystem/s configured for deployment on the chip, each fault injection detection subsystem having plural sensitivity levels which are selectable in real time and comprising at least one hardware fault injection detector circuit/s, configured for deployment on the chip, and/or, coupled thereto, sensitivity level control logic which may be configured for deployment on the chip and which may be operative, in real time, to transition the fault injection detection subsystem, from its current sensitivity level from among said plural selectable sensitivity levels, to a next sensitivity level from among said plural selectable sensitivity levels, e.g. by generating sensitivity control signals (aka sensitivity level selections) and/or feeding the sensitivity control signals to at least one hardware fault injection detector in the subsystem.

Abstract: A system for verifying integrity of content of an integrated circuit's registers, the system being operative in conjunction with an integrated circuit including at least one memory, at least one processor, and a multiplicity of registers, the system comprising register content verification logic configured, when in a first mode aka “Study Mode”, to read at least some of the registers' content, to compute a first hash on the content, and to store the first hash thereby to provide an up-to-date reference hash, and, at least on occasion, when in a second mode aka “Verify Mode”, to compute at least one second hash on the content, to compare the second hash to the reference hash and, accordingly, to provide a content verification output (aka “fault detection” output) indicative of whether the reference and second hashes are equal.

Abstract: A security system dynamically, depending on processor core execution flow, controls fault injection countermeasure circuitry protect processor core from fault injection attacks.

Abstract: A self-correcting memory system comprising an integrated circuit including memory and memory content authentication functionality, which is operative to compare content to be authenticated to a standard and to output “authentic” if the content to be authenticated equals the standard and “non-authentic” otherwise; and error correction functionality which is operative to apply at least one possible correction to at least one erroneous word entity in said memory, yielding a possibly correct word entity, call said authentication for application to the possibly correct word entity, and if the authentication's output is “authentic”, to replace said erroneous word entity in said memory, with said possibly correct word entity thereby to yield error correction at a level of confidence derived from the level of confidence associated with the authentication.

Abstract: System, method and computer program product for prioritizing trial-and-error attempted corrections of bit/s, in a memory, in which logical bit levels are determined by thresholding voltage values using threshold/s, the method comprising ranking bits such that a first bit is ranked before a second bit, which is less likely than said first bit to be erroneous and sequentially attempting to correct the bits in order of the ranking, including attempting to correct the first bit before attempting to correct the second bit.

Abstract: A security device includes an interface and a processor. The interface is configured for connecting to a bus that serves a host device and a non-volatile memory (NVM) device. The processor is connected to the bus in addition to the host device and the NVM device. The processor is configured to detect on the bus a boot process, in which the host device retrieves boot code from the NVM device, and to ascertain a security of the boot process, based on an authentic copy of at least part of the boot code of the host device.

Abstract: A system for improving utilization of a nonvolatile flash memory device which has pages whose guaranteed per-cycle erase time and guaranteed number of cycles are known, the system comprising erase time determination functionality for individual pages; de-facto total erase-time accumulation functionality incrementing, for each erase cycle to which an individual page is subjected, by the individual page's de facto erase time per cycle as provided by the erase time measurement functionality; and flash memory page usage monitoring functionality operative to control usage of pages in flash memory including selecting at least one individual flash memory page depending on a comparison between the individual flash memory page's de facto total erase time and a guaranteed erase time computed as a product of the guaranteed per-cycle erase time and of the guaranteed number of cycles.

Abstract: A security device includes an interface and a processor. The interface is configured for connecting to a bus that serves a host device and a non-volatile memory (NVM) device. The processor is connected to the bus in addition to the host device and the NVM device. The processor is configured to detect on the bus a boot process, in which the host device retrieves boot code from the NVM device, and to ascertain a security of the boot process, based on an authentic copy of at least part of the boot code of the host device.

Abstract: A security system dynamically, depending on processor core execution flow, controls fault injection countermeasure circuitry protect processor core from fault injection attacks.

Abstract: A method of testing an integrated circuit device, which involves receiving, by a processor, a test definition indicating a sequence of acts to be performed by an automated test equipment in testing an integrated circuit device. The test definition includes indications of test cycles and timings of events in the cycles.

Abstract: A method of testing an integrated circuit device, which involves receiving, by a processor, a test definition indicating a sequence of acts to be performed by an automated test equipment in testing an integrated circuit device. The test definition includes indications of test cycles and timings of events in the cycles.

Abstract: A system for improving utilization of a nonvolatile flash memory device which has pages whose guaranteed per-cycle erase time and guaranteed number of cycles are known, the system comprising erase time determination functionality for individual pages; de-facto total erase-time accumulation functionality incrementing, for each erase cycle to which an individual page is subjected, by the individual page's de facto erase time per cycle as provided by the erase time measurement functionality; and flash memory page usage monitoring functionality operative to control usage of pages in flash memory including selecting at least one individual flash memory page depending on a comparison between the individual flash memory page's de facto total erase time and a guaranteed erase time computed as a product of the guaranteed per-cycle erase time and of the guaranteed number of cycles.

Abstract: An input device includes a touch sensor and a processing unit. The touch sensor has a surface and is configured to sense an imprint of a finger that touches the surface. The processing unit is configured to calculate a tilt of the finger relative to the surface by measuring a shift of the imprint sensed by the touch surface, and to produce an output based on the tilt.

Abstract: A method for using a non-timer dedicated resource, such as a communication resource, for performing timing operations is provided. The method is advantageous for use with embedded applications in dedicated devices having limited timing resources, particularly in cases where the existing timing resources have all been allocated to specific tasks and are not available to accommodate further timing requirements.

Abstract: Apparatus for demodulating a train of pulses includes a one-shot device having an asynchronous data input terminal, which is configured to receive the train of pulses, and a one-shot data output terminal. A first clocked logic gate has a first clocked data input terminal, which is coupled to the one-shot data output terminal, and a first clocked data output terminal. A combinatorial logic gate has combinatorial input terminals, which are coupled to the one-shot and first clocked data output terminals, and a combinatorial output terminal. A second clocked logic gate has a second clocked data input terminal, which is coupled to the combinatorial output terminal, and a second clocked data output terminal, which is configured to output a demodulated envelope of the train of pulses.