Abstract: Disclosed embodiments include system including a hardware based, programmable data analytics processor configured to reside between a data storage unit and one or more hosts. The programmable data analytics processor includes a selector module configured to input a first set of data and, based on a selection indicator, output a first subset of the first set of data; a filter and project module configured to input a second set of data and, based on a function, output an updated second set of data; a join and group module configured to combine data from one or more third data sets into a combined data set; and a communications fabric configured to transfer data between any of the selector module, the filter and project module, and the join and group module.

Abstract: A microprocessor includes a function-specific architecture, an interface configured to communicate with an external memory via at least one memory channel, a first architecture block configured to perform a first task associated with a thread, and a second architecture block configured to perform a second task associated with the thread. The second task includes a memory access via the at least one memory channel. The microprocessor further includes a third architecture block configured to perform a third task associated with the thread. The first architecture block, the second architecture block, and the third architecture block are configured to operate in parallel such that the first task, the second task, and the third task are all completed during a single clock cycle associated with the microprocessor.

Abstract: A network device includes a receive processor configured to store, in a packet memory, a payload of a packet received from a communication network. The network device also includes a packet processor configured to modify one or more fields of a header of the packet to generate a modified header, perform egress classification of the packet based on the modified header, and store the modified header in the packet memory. The network device further includes a transmit processor configured to transmit the packet in accordance with the egress classification. The transmit processor is configured to, in response to a decision that the packet is to be transmitted from the network device, generate a transmit packet from the payload retrieved from the packet memory and the modified header retrieved from the packet memory and cause the transmit packet to be transmitted to a destination in the communication network.

Abstract: A system for distributed storage agents includes at least one memory and at least one compute node comprising at least one agent module. The at least one agent module is configured to cause at least a portion of data stored in the at least one memory to be pushed to a destination in accordance with an agent access plan.

Abstract: A network device includes a packet processor that: determines at least one egress port via which a received packet is to be transmitted by the network device; modifies one or more fields in a header of the packet to generate a modified header; determines, based at least in part on the modified header, whether the packet a) is to be transmitted or b) is to be discarded; and stores the modified header in a packet memory. In response to the determination that the packet is to be transmitted, a transmit processor of the network device: retrieves a payload of the packet from the packet memory; retrieves the modified header from the packet memory; generates a transmit packet at least by combining the payload of the packet with the modified header; and transmits the transmit packet via the determined at least one egress port of the network device.

Abstract: Disclosed embodiments include a computational memory system. The computational memory system includes a master controller configured to receive a configuration function from a host CPU and convert the received configuration function into one or more lower level configuration functions. The computational memory system also includes at least one computational memory chip, wherein the at least one computational memory chip includes a plurality of processor subunits and a plurality of memory banks formed on a common substrate. The master controller is adapted to configure the at least one computational memory chip using the one or more lower level configuration functions.

Abstract: Disclosed embodiments include system including a hardware based, programmable data analytics processor configured to reside between a data storage unit and one or more hosts. The programmable data analytics processor includes a selector module configured to input a first set of data and, based on a selection indicator, output a first subset of the first set of data; a filter and project module configured to input a second set of data and, based on a function, output an updated second set of data; a join and group module configured to combine data from one or more third data sets into a combined data set; and a communications fabric configured to transfer data between any of the selector module, the filter and project module, and the join and group module.

Abstract: A network device includes a memory configured to store a plurality of entries in respective locations in the memory, the plurality of entries corresponding to a trie data structure for performing a longest prefix match search. The network device also includes: a memory access engine configured to retrieve from a location in the memory, in a single memory lookup operation, i) longest prefix match information for a node corresponding to a network address in a header of a packet, and ii) pointer information that indicates a child node in the trie data structure. The network device also includes: a child node address calculator configured to use i) the longest prefix match information, and ii) the pointer information, to calculate a memory address of another location in the memory corresponding to the child node.

Abstract: A network device includes a packet processor that: determines at least one egress port via which a received packet is to be transmitted by the network device; modifies one or more fields in a header of the packet to generate a modified header; determines, based at least in part on the modified header, whether the packet a) is to be transmitted or b) is to be discarded; and stores the modified header in a packet memory. In response to the determination that the packet is to be transmitted, a transmit processor of the network device: retrieves a payload of the packet from the packet memory; retrieves the modified header from the packet memory; generates a transmit packet at least by combining the payload of the packet with the modified header; and transmits the transmit packet via the determined at least one egress port of the network device.

Abstract: At least a payload of a packet that is received by a network device is stored in a packet memory. The packet is processed at least to determine at least one egress port via which the packet is to be transmitted, modify a header of the packet to generate a modified header, and determine, based at least in part on the modified header, whether the packet is to be transmitted or to be discarded by the network device. In response to determining that the packet is to be transmitted, the at least the payload of the packet is retrieved from the packet memory, a transmit packet is generated at least by combining the at least the payload of the packet with the modified header, and the transmit packet is transmitted via the determined at least one egress port of the network device.

Abstract: A network switch device is described. The network switch device includes a plurality of processor devices configured to perform different respective functions of the network switch device, a block of shared memory having a plurality of single port memory banks, and a memory controller configured to allocate respective sets of banks among the single port memory banks to processor devices among the plurality of processor devices, and determine respective configurations of the sets of memory banks as one of i) a single port configuration in which respective single port memory banks support a single read or write memory operation to a memory location in a memory access cycle, and ii) a virtual multi-port configuration in which respective single port memory banks support two or more concurrent read or write memory operations to a same memory location, based on memory access requirements of the corresponding processor device.

Abstract: In a network device, a hash-based lookup system includes a hash generator configured to apply respective hash functions to a lookup key to generate respective hash values. Each hash function corresponds to a respective logical hash bank in a hash table. A number of hash values generated by the hash generator corresponds to the number of logical hash banks in the hash table, and the number of hash values generated by the hash generator is configurable. The hash-based lookup system also includes an address generator that is configured to generate respective addresses to a memory that stores the hash table, the respective addresses within respective address spaces of respective logical hash banks of the hash table. The address generator uses i) a parameter N that specifies the number of logical hash banks in the hash table, and ii) N hash values generated by the hash generator, to generate the respective addresses.

Abstract: A packet processor of a network device determines an amount of free buffer space in a buffer memory currently available for buffering packets, and dynamically determines a value of a threshold for triggering a particular traffic management operation with respect to a packet, to dynamically adjust the value of the threshold based at least in part on a changing amount of free buffer space available for buffering packets in the buffer memory. The packet processor determines, based on a comparison between i) a current fill level of a particular transmit queue in which the packet is to be enqueued and ii) the dynamically adjusted value of the threshold, whether the particular traffic management operation is to be triggered with respect to the packet. When the particular traffic management operation is to be triggered, the packet processor performs the particular traffic management operation with respect to the packet.

Abstract: A packet received by a network device via a network. A first portion of the packet is stored in a packet memory, the first portion including at least a payload of the packet. The packet is processed based on information from a header of the packet. After the packet is processed, a second portion of the packet is stored in the packet memory, the second portion including at least a portion of the header of the packet. When the packet is to be transmitted the first portion of the packet and the second portion of the packet are retrieved from the packet memory, and the first portion and the second portion are combined to generate a transmit packet. The transmit packet is forwarded to a port of the network device for transmission of the transmit packet via port of the network device.

Abstract: A packet type corresponding to a packet received by a network device is determined. Based on the packet type, one or more header fields to be extracted from a header of the packet are identified. Identifying the one or more header fields includes extracting, from a memory based on the packet type, respective indicators of locations of the one or more header fields and respective indicators of sizes of the one or more header fields. The one or more identified header fields from the header of the packet, based on the respective indicators of locations of the one or more header fields and respective indicators of sizes of the one or more header fields. The packet is then processed based on the one or more header fields extracted from the header. The processing includes deter mining at least one port to which to forward the packet.

Abstract: At least a payload of a packet that is received by a network device is stored in a packet memory. The packet is processed at least to determine at least one egress port via which the packet is to be transmitted, modify a header of the packet to generate a modified header, and determine, based at least in part on the modified header, whether the packet is to be transmitted or to be discarded by the network device. In response to determining that the packet is to be transmitted, the at least the payload of the packet is retrieved from the packet memory, a transmit packet is generated at least by combining the at least the payload of the packet with the modified header, and the transmit packet is transmitted via the determined at least one egress port of the network device.

Abstract: A packet processor of a network device determines an amount of free buffer space in a buffer memory currently available for buffering packets, and dynamically determines a value of a threshold for triggering a particular traffic management operation with respect to a packet, to dynamically adjust the value of the threshold based at least in part on a changing amount of free buffer space available for buffering packets in the buffer memory. The packet processor determines, based on a comparison between i) a current fill level of a particular transmit queue in which the packet is to be enqueued and ii) the dynamically adjusted value of the threshold, whether the particular traffic management operation is to be triggered with respect to the packet. When the particular traffic management operation is to be triggered, the packet processor performs the particular traffic management operation with respect to the packet.

Abstract: In a method for egress processing packets in a network device, a first stage engine, implemented in hardware, identifies a particular set of computer-readable instructions for a particular packet. The particular set of computer-readable instructions is identified from among a plurality of sets of computer-readable instructions stored in a memory, respective ones of the plurality of sets of computer-readable instructions being for performing different sets of egress processing operations with respect to different packets. A second stage processor, configured to execute computer-readable instructions stored in the memory, executes the particular set of computer-readable instructions, identified by the first stage engine, to perform the corresponding set of egress processing with respect to the particular packet.

Abstract: A packet received by a network device via a network. A first portion of the packet is stored in a packet memory, the first portion including at least a payload of the packet. The packet is processed based on information from a header of the packet. After the packet is processed, a second portion of the packet is stored in the packet memory, the second portion including at least a portion of the header of the packet. When the packet is to be transmitted the first portion of the packet and the second portion of the packet are retrieved from the packet memory, and the first portion and the second portion are combined to generate a transmit packet.

Abstract: A network switch device is described. The network switch device includes a plurality of processor devices configured to perform different respective functions of the network switch device, a block of shared memory having a plurality of single port memory banks, and a memory controller configured to allocate respective sets of banks among the single port memory banks to processor devices among the plurality of processor devices, and determine respective configurations of the sets of memory banks as one of i) a single port configuration in which respective single port memory banks support a single read or write memory operation to a memory location in a memory access cycle, and ii) a virtual multi-port configuration in which respective single port memory banks support two or more concurrent read or write memory operations to a same memory location, based on memory access requirements of the corresponding processor device.