Abstract: A method is provided for writing a data word to a resistive memory consisting of 2T2R differential cells each having first and second sets of a resistor (R) and a selection transistor (T). The method includes generating an initial codeword, programming it in 1T1R mode, checking its programming in 1T1R mode, inverting it, programming the inverted initial codeword in 1T1R mode, checking its programming in 1T1R mode, and reading, in 2T2R differential mode, that the read data correspond to said initial data. A device designed to implement this write method and to an electronic system including this device is also provided.

Abstract: A resistive random-access memory (ReRAM) array with parallel reset and set programming and a method for programming is presented. The ReRAM array includes a plurality of ReRAM cells arranged in an array, wherein the array includes a plurality of rows and a plurality of columns, wherein at least two ReRAM cells of an array includes a word, wherein each ReRAM cell includes a select device having a control port, a first port, and a second port, and a resistive element; and a plurality of controllers, wherein the output of each of the plurality of controllers cause a reset programming or a set programming of the ReRAM cell in the column of the plurality of ReRAM cells that has the respective word line activated; such that the reset programming and the set programming occur in parallel.

Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

Abstract: Reference generator circuitry for providing a reference to sense amplifiers in a flash memory device. The circuitry includes a reference current generator for generating a reference current for use by the sense amplifier circuits. A current buffer circuit in the flash memory device mirrors the reference current and applies a plurality of mirrored reference currents to the reference inputs of the sense amplifiers. A startup circuit is utilized in order to provide a fast settling time of the reference node appearing at the input of the sense amplifiers. The startup circuit includes first and second discharge current stages, with the first discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon a bandgap reference current. The second discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon the reference current.

Abstract: A sense amplifier circuit and method are disclosed for nonvolatile memory devices, such as flash memory devices. The sense amplifier circuit includes a current source that is configurable to source any of at least two nonzero current levels in the sense amplifier circuit. The sense amplifier circuit is controlled by control circuitry in the nonvolatile memory device so that each sense amplifier circuit sources a first current level during the precharge cycle of a memory read operation, and a second current level, greater than the first current level, during the memory cell sense operation. In this way, the sense amplifier circuit consumes less power during the memory read operation without an appreciable loss in performance.

Abstract: A sense amplifier circuit and method are disclosed for nonvolatile memory devices, such as flash memory devices. The sense amplifier circuit includes a current source that is configurable to source any of at least two nonzero current levels in the sense amplifier circuit. The sense amplifier circuit is controlled by control circuitry in the nonvolatile memory device so that each sense amplifier circuit sources a first current level during the precharge cycle of a memory read operation, and a second current level, greater than the first current level, during the memory cell sense operation. In this way, the sense amplifier circuit consumes less power during the memory read operation without an appreciable loss in performance.

Abstract: Reference generator circuitry for providing a reference to sense amplifiers in a flash memory device. The circuitry includes a reference current generator for generating a reference current for use by the sense amplifier circuits. A current buffer circuit in the flash memory device mirrors the reference current and applies a plurality of mirrored reference currents to the reference inputs of the sense amplifiers. A startup circuit is utilized in order to provide a fast settling time of the reference node appearing at the input of the sense amplifiers. The startup circuit includes first and second discharge current stages, with the first discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon a bandgap reference current. The second discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon the reference current.

Abstract: A sense amplifier circuit and method are disclosed for nonvolatile memory devices, such as flash memory devices. The sense amplifier circuit includes a current source that is configurable to source any of at least two nonzero current levels in the sense amplifier circuit. The sense amplifier circuit is controlled by control circuitry in the nonvolatile memory device so that each sense amplifier circuit sources a first current level during the precharge cycle of a memory read operation, and a second current level, greater than the first current level, during the memory cell sense operation. In this way, the sense amplifier circuit consumes less power during the memory read operation without an appreciable loss in performance.

Abstract: A programmable logic device includes a plurality of logic elements. Each logic element includes a raw of transistors formed between a bit line and a source line, elements for generating a complement signal to the bit line signal (the elements have an output complement line) and a differential sense amplifier. Each transistor of the row is connected to a different one of the input lines and has a predefined logic state. The complement line is based on the source line whose signal acts opposite to that of the bit line. The differential sense amplifier is connected to the bit line and to the complement line and indicates when the bit line signal crosses the complement line signal. In one embodiment, the source line signal is raised, in another, the bit line signal is lowered, both with offset circuitry.