Abstract: A forwarding table comprising a combination of a hash table and a content addressable memory (CAM). The forwarding table combines a one way hash table and a small CAM to perform the forwarding information retrieval function. The CAM is used when an address cannot be found in the hash table. When MAC addresses are being added to the forwarding table, they are first tried in the hash table. The address is applied to the hash function and a resulting index input to the hash table. If a hit occurs, it indicates that an entry at that index already exists and a location in the CAM is then allocated for that address. As long as the CAM does not become full, a 100% hit rate is guaranteed. During retrieval, the hash table or the CAM forms the forwarding information output to the next processing stage. If an entry is not found in the hash table, it will typically be found in the CAM. If no entry is found in either, the received frame is flooded to all the ports of the network device.

Abstract: A dynamic queuing system wherein a single memory is shared among a plurality of different queues. A single memory, termed a queue memory, is by ally shared by one or more queue. The queue memory is divided into a plurality of memory blocks that we initially empty. An empty list functions to track which memory blocks are empty and available for use in a queue. Each queue constructed utilizes one or more memory blocks. When a queue becomes full, an additional memory block is allocated to it. Conversely, as memory blocks of a queue are read, i.e. emptied, they are returned to the pool of empty memory blocks for use by other queued.

Abstract: An apparatus and method for providing synchronization in a data transmission system via the use of a short cyclic synchronization sequence inserted in the header of cells to be transmitted. A 2-bit sync sequence is inserted at the beginning of the header in each cell. At the receiving end, a pair of state machines search for and track the sync sequence. A feedback signal is generated that is used by the receiver to adjust its framing so as to align the received data with the boundaries of the cells. To aid in detecting the sync sequence, the two sync bits are rotated each cell cycle. To avoid confusion with data that mimics the sync sequence, the transmitter transmits idle cells containing all ones except for the 2-bit sync sequence field during the period that the receiver is attempting to sync up with the transmitter.

Abstract: A queue having a ‘duplicate’ counter associated with each entry whereby duplicate data is not stored in the queue. Before data is placed in the queue, the queue is searched for an entry matching the data to be written. If a match is found, the duplicate counter associated with the entry is incremented. Further, if a match is found and the data stored therein is inconsistent with the current data, the contents of the queue are updated and the duplicate counter associated with the entry is reset to one. If a match is not found, the data is written to the queue and the duplicate counter associated with the entry is initialized to one.

Abstract: An apparatus for and a method of compressing the forwarding decision for a frame within a network device. A forwarding decision is compressed yielding a forwarding pointer that occupies far less memory space than the corresponding output port vector. The compressed forwarding pointers are stored in a forwarding table that is accessed using a hash function. A forwarding CAM is used to resolve conflicts in the hash table. The output port vectors are stored in an output port vector table that comprises a relatively small number of possible combinations of the port vector. A forwarding decision is made for each received frame by a forwarding processor in the device. The forwarding decision is represented by a compressed forwarding pointer that is stored in a table and associated with the received frame. At some later point in time, the frame is output to one or more destination ports in accordance with a corresponding output port vector.

Abstract: A traffic management unit for implementing Traffic Management (TM) of Available Bit Rate (ABR) traffic on an Asynchronous Transfer Mode (ATM) network is described. The traffic management unit comprises a traffic management processor coupled to a traffic management memory. The traffic management processor is coupled between a data processor and an ATM interface. An Ethernet workstation is coupled to the data processor through an Ethernet interface. An ATM switch is coupled to the traffic management processor through the ATM interface. The traffic management unit is implemented as a unit separate from the cell scheduling data processor. In addition, in order to utilize network congestion information more efficiently, VCs are grouped according to their output destinations or their path through the network. Congestion feedback for one VC is applied to other VCs within the group.

Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.

Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.

Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.