Abstract: Systems and methods parse integrated circuit (IC) design files to identify boundary conditions between components. The boundary conditions may correspond to connections between different components, at various levels of the IC, that may create antennas during one or more manufacturing processes. The identified boundary conditions may be extracted from the design files to generate lighter weight design files that eliminate parameters that are not associated with the boundary conditions. Design files for each component within a system may be parsed and checked for boundary conditions prior to delivery and integration to a top level design file. Thereafter, the top level may be executed with a run-set, such as to perform an antenna check.

Abstract: A voltage droop detection circuit can be used to detect a voltage droop in an integrated circuit (IC) device. The voltage droop detection circuit may include a chain of inverting stages, and each inverting stage may include a P-type transistor and an N-type transistor. The chain of inverting stages can be initialized to alternating logic states during an initialization phase of a clock cycle, and an evaluation pulse can be inputted into the chain of inverting stages during an evaluation phase of the clock cycle. A voltage droop may be detected if a number of inverting stages that are able to switch output logic states from their respective initialized logic states is smaller than a nominal value indicating a number of inverting stages that are able to switch their respective output logic states under normal voltage condition.