Patents by Inventor Ilan TSAMERET

Ilan TSAMERET has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Antifuse memory arrays with antifuse elements at the back-end-of-line (BEOL)
    Patent number: 11264317
    Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Vincent Dorgan, Jeffrey Hicks, Miriam Reshotko, Abhishek Sharma, Ilan Tsameret
  • ANTIFUSE MEMORY ARRAYS WITH ANTIFUSE ELEMENTS AT THE BACK-END-OF-LINE (BEOL)
    Publication number: 20190304894
    Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Vincent DORGAN, Jeffrey HICKS, Miriam RESHOTKO, Abhishek SHARMA, Ilan TSAMERET