Abstract: A comparator system may include a comparator circuit and input circuitry coupled to a communication line. The circuitry may include resistors that are used to generate input voltages supplied to input terminals of the comparator. Resistor-dependent currents generated from a resistor-dependent current source may be supplied to the resistors of the input circuitry. The resistors of the input circuitry and resistors of the resistor-dependent current source may be of the same type and/or configured on the same chip to increase stability in the presence of various process-voltage-temperature (PVT) conditions. The comparator system may be implemented as a squelch detector or other signal detection system, such that an output generated by the comparator based on the input voltages may indicate presence or absence of a signal.

Abstract: A method of controlling the operations of an on-chip memory unit includes the steps of receiving an indication of at least the ready or busy state of the memory unit and instructing the memory unit to perform the next operation once the indication is of the ready state. The step of receiving can include the repeated steps of capturing the indication and the data and address information of the previous byte provided to the memory unit and shifting the data and address information of a next byte and at least one extra bit through a shift register such that the indication is also shifted out of the shift register to a data out pin of a JTAG port. The steps of capturing and shifting, which provide double buffering, are repeated until the indication is of the ready state. Alternatively, the step of receiving occurs from a non-JTAG port of the chip to a pin on a receiving port. The present invention includes the chip which can operate according to the steps of the method.