Patents by Inventor Ilaria Gelmi
Ilaria Gelmi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11945712Abstract: A process for manufacturing a MEMS device includes forming a first structural layer of a first thickness on a substrate. First trenches are formed through the first structural layer, and masking regions separated by first openings are formed on the first structural layer. A second structural layer of a second thickness is formed on the first structural layer in direct contact with the first structural layer at the first openings and forms, together with the first structural layer, thick structural regions having a third thickness equal to the sum of the first and the second thicknesses. A plurality of second trenches are formed through the second structural layer, over the masking regions, and third trenches are formed through the first and the second structural layers by removing selective portions of the thick structural regions.Type: GrantFiled: May 14, 2021Date of Patent: April 2, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Giorgio Allegato, Lorenzo Corso, Ilaria Gelmi, Carlo Valzasina
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Publication number: 20220169498Abstract: A semiconductor device includes: a substrate; a transduction microstructure integrated in the substrate; a cap joined to the substrate and having a first face adjacent to the substrate and a second, outer, face; and a channel extending through the cap from the second face to the first face and communicating with the transduction microstructure. A protective membrane made of porous polycrystalline silicon permeable to aeriform substances is set across the channel.Type: ApplicationFiled: November 23, 2021Publication date: June 2, 2022Applicants: STMICROELECTRONICS S.R.L., STMicroelectronics International N.V.Inventors: Enri DUQI, Lorenzo BALDO, Paolo FERRARI, Benedetto Vigna, Flavio Francesco VILLA, Laura Maria CASTOLDI, Ilaria GELMI
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Publication number: 20210363000Abstract: A process for manufacturing a MEMS device includes forming a first structural layer of a first thickness on a substrate. First trenches are formed through the first structural layer, and masking regions separated by first openings are formed on the first structural layer. A second structural layer of a second thickness is formed on the first structural layer in direct contact with the first structural layer at the first openings and forms, together with the first structural layer, thick structural regions having a third thickness equal to the sum of the first and the second thicknesses. A plurality of second trenches are formed through the second structural layer, over the masking regions, and third trenches are formed through the first and the second structural layers by removing selective portions of the thick structural regions.Type: ApplicationFiled: May 14, 2021Publication date: November 25, 2021Applicant: STMicroelectronics S.r.l.Inventors: Giorgio ALLEGATO, Lorenzo CORSO, Ilaria GELMI, Carlo VALZASINA
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Patent number: 10322931Abstract: A transducer includes a first substrate and an integrated circuit coupled to the first substrate. A sensor is electrically coupled to the integrated circuit and includes a second substrate having a first surface and a second surface opposite the first surface. The second substrate has scribe boundaries defining an outer edge of the second substrate and a chamber extending from the first surface towards but not reaching the second surface. A chamber extends from the second surface to meet the chamber from first surface. Scribe trenches in the second surface at the scribe boundaries have a width from the scribe boundary towards the chamber extending from the second surface. A membrane extends over the first surface and over the chamber extending from first surface. A plate extends from the first surface of the second substrate over the membrane.Type: GrantFiled: July 17, 2017Date of Patent: June 18, 2019Assignee: STMicroelectronics S.r.l.Inventors: Matteo Perletti, Pietro Petruzza, Ilaria Gelmi, Laura Maria Castoldi
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Publication number: 20170313582Abstract: A transducer includes a first substrate and an integrated circuit coupled to the first substrate. A sensor is electrically coupled to the integrated circuit and includes a second substrate having a first surface and a second surface opposite the first surface. The second substrate has scribe boundaries defining an outer edge of the second substrate and a chamber extending from the first surface towards but not reaching the second surface. A chamber extends from the second surface to meet the chamber from first surface. Scribe trenches in the second surface at the scribe boundaries have a width from the scribe boundary towards the chamber extending from the second surface. A membrane extends over the first surface and over the chamber extending from first surface. A plate extends from the first surface of the second substrate over the membrane.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Matteo Perletti, Pietro Petruzza, Ilaria Gelmi, Laura Maria Castoldi
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Patent number: 9731965Abstract: A method of forming semiconductor devices, such as capacitive type MEMS acoustic transducers, in a semiconductor includes forming a mask layer on a back surface of the semiconductor wafer and removing first etch portions of the mask layer and scribe trench portions of the mask layer. Each scribe trench portion is positioned in the mask layer to define a corresponding scribe boundary of a plurality of the semiconductor devices being formed in the semiconductor wafer. Etching the semiconductor wafer through the first etch portions and the scribe trench portions may be done simultaneously to form external back chambers and scribe trenches, respectively, in the semiconductor wafer. The semiconductor wafer is then cut along cutting lines in the scribe trenches to singulate individual MEMS acoustic transducers. The etching through the first and second etch portions and the scribe trench portions are dry etching of the semiconductor substrate in one embodiment.Type: GrantFiled: March 31, 2016Date of Patent: August 15, 2017Assignee: STMICROELECTRONICS S.R.L.Inventors: Matteo Perletti, Pietro Petruzza, Ilaria Gelmi, Laura Maria Castoldi
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Patent number: 8486741Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.Type: GrantFiled: May 25, 2012Date of Patent: July 16, 2013Assignee: STMicroelectronics S.r.l.Inventors: Pietro Montanini, Giovanna Germani, Ilaria Gelmi, Marta Mottura
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Patent number: 8344466Abstract: A process for manufacturing a MEMS device, wherein a bottom silicon region is formed on a substrate and on an insulating layer; a sacrificial region of dielectric is formed on the bottom region; a membrane region, of semiconductor material, is epitaxially grown on the sacrificial region; the membrane region is dug down to the sacrificial region so as to form through apertures; the side wall and the bottom of the apertures are completely coated in a conformal way with a porous material layer; at least one portion of the sacrificial region is selectively removed through the porous material layer and forms a cavity; and the apertures are filled with filling material so as to form a monolithic membrane suspended above the cavity. Other embodiments are directed to MEMS devices and pressure sensors.Type: GrantFiled: August 4, 2010Date of Patent: January 1, 2013Assignee: STMicroelectronics S.r.l.Inventors: Pietro Corona, Stefano Losa, Ilaria Gelmi, Roberto Campedelli
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Publication number: 20120228260Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.Type: ApplicationFiled: May 25, 2012Publication date: September 13, 2012Applicant: STMicroelectronics S.r.I.Inventors: Pietro MONTANINI, Giovanna GERMANI, Ilaria GELMI, Marta MOTTURA
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Publication number: 20110031567Abstract: A process for manufacturing a MEMS device, wherein a bottom silicon region is formed on a substrate and on an insulating layer; a sacrificial region of dielectric is formed on the bottom region; a membrane region, of semiconductor material, is epitaxially grown on the sacrificial region; the membrane region is dug down to the sacrificial region so as to form through apertures; the side wall and the bottom of the apertures are completely coated in a conformal way with a porous material layer; at least one portion of the sacrificial region is selectively removed through the porous material layer and forms a cavity; and the apertures are filled with filling material so as to form a monolithic membrane suspended above the cavity.Type: ApplicationFiled: August 4, 2010Publication date: February 10, 2011Applicant: STMICROELECTRONICS S.R.L.Inventors: Pietro Corona, Stefano Losa, Ilaria Gelmi, Roberto Campedelli
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Publication number: 20060068554Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.Type: ApplicationFiled: September 19, 2005Publication date: March 30, 2006Inventors: Pietro Montanini, Giovanna Germani, Ilaria Gelmi, Marta Mottura
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Patent number: 6696364Abstract: A method for manipulating MEMS devices integrated on a semiconductor wafer and intended to be diced one from the other includes bonding of the semiconductor wafer including the MEMS devices on a support with interposition of a bonding sheet. The method may also include completely cutting or dicing of the semiconductor wafer into a plurality of independent MEMS devices, and processing the MEMS devices diced and bonded on the support in a treatment environment for semiconductor wafers. A support for manipulating MEMS devices is also included.Type: GrantFiled: August 8, 2002Date of Patent: February 24, 2004Assignee: STMicroelectronics S.r.l.Inventors: Ilaria Gelmi, Simone Sassolini, Stefano Pozzi, Massimo Garavaglia
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Publication number: 20030077881Abstract: A method for manipulating MEMS devices integrated on a semiconductor wafer and intended to be diced one from the other includes bonding of the semiconductor wafer including the MEMS devices on a support with interposition of a bonding sheet. The method may also include completely cutting or dicing of the semiconductor wafer into a plurality of independent MEMS devices, and processing the MEMS devices diced and bonded on the support in a treatment environment for semiconductor wafers. A support for manipulating MEMS devices is also included.Type: ApplicationFiled: August 8, 2002Publication date: April 24, 2003Applicant: STMicroelectronics S.r.l.Inventors: Ilaria Gelmi, Simone Sassolini, Stefano Pozzi, Massimo Garavaglia
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Patent number: 6395618Abstract: The method is based on the use of an etching mask comprising silicon carbide or titanium nitride for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region of silicon oxide on a substrate of semiconductor material; growing a pseudo-epitaxial layer; forming electronic circuit components; depositing a masking layer comprising silicon carbide or titanium nitride; defining photolithographically the masking layer so as to form an etching mask containing the topography of a microstructure to be formed; with the etching mask, forming trenches in the pseudo-epitaxial layer as far as the sacrificial region so as to laterally define the microstructure; and removing the sacrificial region through the trenches.Type: GrantFiled: December 19, 2000Date of Patent: May 28, 2002Assignee: STMicroelectronics S.r.l.Inventors: Paolo Vergani, Ilaria Gelmi, Pietro Montanini, Marco Ferrera, Laura Castoldi
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Publication number: 20010026951Abstract: The method is based on the use of an etching mask comprising silicon carbide or titanium nitride for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region of silicon oxide on a substrate of semiconductor material; growing a pseudo-epitaxial layer; forming electronic circuit components; depositing a masking layer comprising silicon carbide or titanium nitride; defining photolithographically the masking layer so as to form an etching mask containing the topography of a microstructure to be formed; with the etching mask, forming trenches in the pseudo-epitaxial layer as far as the sacrificial region so as to laterally define the microstructure; and removing the sacrificial region through the trenches.Type: ApplicationFiled: December 19, 2000Publication date: October 4, 2001Inventors: Paolo Vergani, Ilaria Gelmi, Pietro Montanini, Marco Ferrera, Laura Castoldi
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Patent number: 6197655Abstract: The method is based on the use of a silicon carbide mask for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region of silicon oxide on a substrate of semiconductor material; growing a pseudo-epitaxial layer; forming electronic circuit components; depositing a silicon carbide layer; defining photolithographically the silicon carbon layer so as to form an etching mask containing the topography of a microstructure to be formed; with the etching mask, forming trenches in the pseudo-epitaxial layer as far as the sacrificial region so as to laterally define the microstructure; and removing the sacrificial region through the trenches.Type: GrantFiled: July 10, 1998Date of Patent: March 6, 2001Assignee: STMicroelectronics S.r.l.Inventors: Pietro Montanini, Marco Ferrera, Laura Castoldi, Ilaria Gelmi