Patents by Inventor Il-Gweon Kim
Il-Gweon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11903184Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.Type: GrantFiled: August 3, 2021Date of Patent: February 13, 2024Inventors: Kyung Hwan Lee, Yong Seok Kim, Il Gweon Kim, Hui-Jung Kim, Min Hee Cho, Jae Ho Hong
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Publication number: 20220199625Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.Type: ApplicationFiled: August 3, 2021Publication date: June 23, 2022Inventors: Kyung Hwan Lee, Yong Seok Kim, Il Gweon Kim, Hui-Jung Kim, Min Hee Cho, Jae Ho Hong
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Publication number: 20220157887Abstract: A three-dimensional semiconductor memory device is provided. The semiconductor memory device includes first horizontal conductive lines on a substrate in a first direction, each of the first horizontal conductive lines extending in a second direction different from the first direction, second horizontal conductive lines stacked on the substrate in the first direction, each of the second horizontal conductive lines extending in the second direction, a vertical conductive line between the first horizontal conductive line and the second horizontal conductive line and extending in the first direction, a plurality of first magnetic tunnel junction patterns between the vertical conductive line and each of the first horizontal conductive lines, and a plurality of second magnetic tunnel junction patterns between the vertical conductive lines and each of the second horizontal conductive lines.Type: ApplicationFiled: July 20, 2021Publication date: May 19, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Kyung Hwan LEE, Kwang Seok KIM, Yong Seok KIM, Il Gweon KIM, Kil Ho LEE
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Publication number: 20220139948Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.Type: ApplicationFiled: July 16, 2021Publication date: May 5, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Kyung Hwan LEE, Yong Seok KIM, Il Gweon KIM, Hyun Cheol KIM, Hyeoung Won SEO, Sung Won YOO, Jae Ho HONG
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Patent number: 7732853Abstract: Nonvolatile integrated circuit memory devices having a 2-bit memory cell include a substrate, a source region and a drain region in the substrate, a step recess channel between the source region and the drain region, a trapping structure including a plurality of charge trapping nano-crystals on the step recess channel, and a gate on the trapping structure. Related fabrication methods are also described.Type: GrantFiled: July 18, 2006Date of Patent: June 8, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Il-gweon Kim
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Publication number: 20100109055Abstract: MOS transistors having an optimized channel plane orientation are provided. The MOS transistors include a semiconductor substrate having a main surface of a (100) plane. An isolation layer is provided in a predetermined region of the semiconductor substrate to define an active region. A source region and a drain region are disposed in the active region. The source and drain regions are disposed on a straight line parallel to a <100> orientation. An insulated gate electrode is disposed over a channel region between the source and drain regions. Methods of fabricating the MOS transistors are also provided.Type: ApplicationFiled: January 8, 2010Publication date: May 6, 2010Inventor: Il-Gweon Kim
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Publication number: 20070069255Abstract: MOS transistors having an optimized channel plane orientation are provided. The MOS transistors include a semiconductor substrate having a main surface of a (100) plane. An isolation layer is provided in a predetermined region of the semiconductor substrate to define an active region. A source region and a drain region are disposed in the active region. The source and drain regions are disposed on a straight line parallel to a <100> orientation. An insulated gate electrode is disposed over a channel region between the source and drain regions. Methods of fabricating the MOS transistors are also provided.Type: ApplicationFiled: August 22, 2006Publication date: March 29, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Il-Gweon KIM
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Publication number: 20070057313Abstract: Nonvolatile integrated circuit memory devices having a 2-bit memory cell include a substrate, a source region and a drain region in the substrate, a step recess channel between the source region and the drain region, a trapping structure including a plurality of charge trapping nano-crystals on the step recess channel, and a gate on the trapping structure. Related fabrication methods are also described.Type: ApplicationFiled: July 18, 2006Publication date: March 15, 2007Inventor: Il-gweon Kim
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Publication number: 20060284241Abstract: Non-volatile memory cells (e.g., EEPROM cells) utilize floating gate electrodes that are each defined by a plurality of spaced-apart semiconductor nanocrystals. Each of the memory cells includes a semiconductor substrate having a tunnel dielectric layer thereon. A plurality of semiconductor nanocrystals are provided on the tunnel dielectric layer. These plurality of semiconductor nanocrystals operate collectively as a floating gate electrode. Each of the semiconductor nanocrystals is encapsulated in a respective fluorinated dielectric layer. A control dielectric layer is provided on the plurality of semiconductor nanocrystals and an electrically conductive control electrode is provided on the control dielectric layer.Type: ApplicationFiled: March 7, 2006Publication date: December 21, 2006Inventor: Il-Gweon Kim
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Patent number: 6734105Abstract: A method for forming silicon quantum dots and a method for fabricating a nonvolatile memory device using the same, suitable for high speed and high packing density. The method for forming silicon quantum dots includes the steps of forming a first insulating film on a semiconductor substrate, forming a plurality of nano-crystalline silicons on the first insulating film, forming a second insulating film on the first insulating film including the nano-crystalline silicons, partially etching the second insulating film and the nano-crystalline silicons, and oxidizing surfaces of the nano-crystalline silicons.Type: GrantFiled: November 15, 2001Date of Patent: May 11, 2004Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Il Gweon Kim
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Patent number: 6649966Abstract: A method for fabricating a quantum dot, which can be used to fabricate a single electron memory device. The method includes forming a first insulation layer on a semiconductor layer, then forming a second insulation layer on the first insulation layer. Next, the second insulation layer is patterned to form an opening to partially expose the upper surface of the first insulation layer. Using the opening in the second insulation layer, a silicon ion is then implanted into the first insulation layer through the opening by using a tilt angle ion implantation method. Finally, the semiconductor layer is treated to re-crystallize the silicon ion implanted into the first insulation layer.Type: GrantFiled: October 7, 2002Date of Patent: November 18, 2003Assignee: Hynix Semiconductor Inc.Inventor: Il-Gweon Kim
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Publication number: 20030054624Abstract: A method for fabricating a quantum dot, which can be used to fabricate a single electron memory device. The method includes forming a first insulation layer on a semiconductor layer, then forming a second insulation layer on the first insulation layer. Next, the second insulation layer is patterned to form an opening to partially expose the upper surface of the first insulation layer. Using the opening in the second insulation layer, a silicon ion is then implanted into the first insulation layer through the opening by using a tilt angle ion implantation method. Finally, the semiconductor layer is treated to re-crystallize the silicon ion implanted into the first insulation layer.Type: ApplicationFiled: October 7, 2002Publication date: March 20, 2003Applicant: Hynix Semiconductor Inc.Inventor: Il-Gweon Kim
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Patent number: 6524883Abstract: A method for fabricating a quantum dot, which can be used to fabricate a single electron memory device. The method includes forming a first insulation layer on a semiconductor layer, then forming a second insulation layer on the first insulation layer. Next, the second insulation layer is patterned to form an opening to partially expose the upper surface of the first insulation layer. Using the opening in the second insulation layer, a silicon ion is then implanted into the first insulation layer through the opening by using a tilt angle ion implantation method. Finally, the semiconductor layer is treated to re-crystallize the silicon ion implanted into the first insulation layer.Type: GrantFiled: August 15, 2001Date of Patent: February 25, 2003Assignee: Hynix Semiconductor Inc.Inventor: Il-Gweon Kim
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Publication number: 20020187566Abstract: A method for gettering a semiconductor device, including steps of growing ingot by an ingot growth method having a pulling speed over 1.5 mm/min and a cooling ratio over 5.0° C./min to form a silicon wafer; and proceeding denudation thermal budget at the silicon wafer, wherein the proceeding denudation thermal budget comprising: forming a trench in the annealed silicon wafer; annealing the trench at about 900 to 1070° C. for about 45 to 90 minutes; filling an HDP oxide film in the trench, and annealing the HDP oxide film at about 900 to 1070° C. for about 45 to 90 minutes; performing a sacrificial oxidation process on the HDP oxide film at about 950 to 1070° C. for about 45 to 90 minutes; and performing a well ion implant process on the annealed silicon wafer, and annealing the resultant wafer at about 950 to 1070° C. for about 45 to 90 minutes.Type: ApplicationFiled: December 7, 2001Publication date: December 12, 2002Inventor: Il Gweon Kim
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Publication number: 20020068457Abstract: A method for forming silicon quantum dots and a method for fabricating a nonvolatile memory device using the same, suitable for high speed and high packing density. The method for forming silicon quantum dots includes the steps of forming a first insulating film on a semiconductor substrate, forming a plurality of nano-crystalline silicons on the first insulating film, forming a second insulating film on the first insulating film including the nano-crystalline silicons, partially etching the second insulating film and the nano-crystalline silicons, and oxidizing surfaces of the nano-crystalline silicons.Type: ApplicationFiled: November 15, 2001Publication date: June 6, 2002Applicant: Hyundai Electronics Industries Co., Ltd.Inventor: Il Gweon Kim
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Publication number: 20020031649Abstract: A method for fabricating a quantum dot, which can be used to fabricate a single electron memory device. The method includes forming a first insulation layer on a semiconductor layer, then forming a second insulation layer on the first insulation layer. Next, the second insulation layer is patterned to form an opening to partially expose the upper surface of the first insulation layer. Using the opening in the second insulation layer, a silicon ion is then implanted into the first insulation layer through the opening by using a tilt angle ion implantation method. Finally, the semiconductor layer is treated to re-crystallize the silicon ion implanted into the first insulation layer.Type: ApplicationFiled: August 15, 2001Publication date: March 14, 2002Applicant: Hynix Semiconductor. Inc.Inventor: Il-Gweon Kim