Patents by Inventor Ilhami Torunoglu

Ilhami Torunoglu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230064987
    Abstract: This application discloses a computing system implementing a mask synthesis system to generate synthetic image clips of design shapes and corresponding mask data for the synthetic image clips. The mask data can describe lithographic masks capable of being used to fabricate the design shapes on an integrated circuit. The mask synthesis system can utilize the synthetic image clips of the design shapes and the corresponding mask data to train a machine-learning system to determine pixelated output masks from portions of the layout design. The mask synthesis system can identify one or more pixelated output masks for portions of a layout design describing an electronic system using the trained machine-learning. The mask synthesis system can synthesize a mask layout design for the electronic system based, at least in part, on the layout design describing the electronic system and the one or more pixelated output masks for the layout design.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Nataraj Akkiraju, Ilhami Torunoglu
  • Publication number: 20220067426
    Abstract: Systems and methods for semi-supervised hotspot detection and classification are disclosed. Hotspots comprise layout pattern that induce printability issues in the lithography process. To detect hotspots, one feature vector, such as an n-dimensional feature vector, is compared with other feature vector(s). The comparison between feature vectors may comprise determining a distance, such as a Euclidian distance, in order to determine closeness between the feature vectors. For example, a training dataset, that includes known hotspots and known non-hotspots, is used in order to determine threshold(s). In particular, for one, some, or all of the known hotspots in the training dataset, a distance to a closest known hotspot and a closest known non-hotspot may be calculated to determine the threshold(s).
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Inventors: Mohamed Bahnas, Ilhami Torunoglu
  • Patent number: 7450220
    Abstract: TOF system shutter time needed to acquire image data in a time-of-flight (TOF) system that acquires consecutive images is reduced, thus decreasing the time in which relative motion can occur. In one embodiment, pixel detectors are clocked with multi-phase signals and integration of the four signals occurs simultaneously to yield four phase measurements from four pixel detectors within a single shutter time unit. In another embodiment, phase measurement time is reduced by a factor (1/k) by providing super pixels whose collection region is increased by a factor “k” relative to a normal pixel detector. Each super pixel is coupled to k storage units and four-phase sequential signals. Alternatively, each pixel detector can have k collector regions, k storage units, and share common clock circuitry that generates four-phase signals. Various embodiments can reduce the mal-effects of clock signal transients upon signals, and can be dynamically reconfigured as required.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: November 11, 2008
    Assignee: Canesta, Inc
    Inventors: Patrick O'Connor, Ilhami Torunoglu, Rajeev Nagabhirana
  • Patent number: 7408627
    Abstract: A method and system dynamically calculates confidence levels associated with accuracy of Z depth information obtained by a phase-shift time-of-flight (TOF) system that acquires consecutive images during an image frame. Knowledge of photodetector response to maximum and minimum detectable signals in active brightness and total brightness conditions is known a priori and stored. During system operation brightness threshold filtering and comparing with the a priori data permits identifying those photodetectors whose current output signals are of questionable confidence. A confidence map is dynamically generated and used to advise a user of the system that low confidence data is currently being generated. Parameter(s) other than brightness may also or instead be used.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: August 5, 2008
    Assignee: Canesta, Inc.
    Inventors: Cyrus Bamji, Ilhami Torunoglu, Salih Burak Gokturk
  • Publication number: 20080036996
    Abstract: TOF system shutter time needed to acquire image data in a time-of-flight (TOF) system that acquires consecutive images is reduced, thus decreasing the time in which relative motion can occur. In one embodiment, pixel detectors are clocked with multi-phase signals and integration of the four signals occurs simultaneously to yield four phase measurements from four pixel detectors within a single shutter time unit. In another embodiment, phase measurement time is reduced by a factor (1/k) by providing super pixels whose collection region is increased by a factor “k” relative to a normal pixel detector. Each super pixel is coupled to k storage units and four-phase sequential signals. Alternatively, each pixel detector can have k collector regions, k storage units, and share common clock circuitry that generates four-phase signals. Various embodiments can reduce the mal-effects of clock signal transients upon signals, and can be dynamically reconfigured as required.
    Type: Application
    Filed: October 16, 2007
    Publication date: February 14, 2008
    Inventors: Patrick O'Connor, Ilhami Torunoglu, Rajeev Nagabhirana
  • Patent number: 7283213
    Abstract: TOF system shutter time needed to acquire image data in a time-of-flight (TOF) system that acquires consecutive images is reduced, thus decreasing the time in which relative motion can occur. In one embodiment, pixel detectors are clocked with multi-phase signals and integration of the four signals occurs simultaneously to yield four phase measurements from four pixel detectors within a single shutter time unit. In another embodiment, phase measurement time is reduced by a factor (1/k) by providing super pixels whose collection region is increased by a factor “k” relative to a normal pixel detector. Each super pixel is coupled to k storage units and four-phase sequential signals. Alternatively, each pixel detector can have k collector regions, k storage units, and share common clock circuitry that generates four-phase signals. Various embodiments can reduce the mal-effects of clock signal transients upon signals, and can be dynamically reconfigured as required.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: October 16, 2007
    Assignee: Canesta, Inc.
    Inventors: Patrick O'Connor, Ilhami Torunoglu, Rajeev Nagabhirana
  • Publication number: 20070130559
    Abstract: Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute the OPC method steps.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 7, 2007
    Applicant: GAUDA, INC.
    Inventors: Ilhami Torunoglu, Ahmet Karakas
  • Patent number: 7151530
    Abstract: A system and method for determining which key value in a set of key values is to be assigned as a current key value as a result an object intersecting a region where a virtual interface is provided. The virtual interface may enable selection of individual key values in the set. The position is determined using a depth sensor that determines a depth of the position in relation to the location of the depth sensor. A set of previous key values that are pertinent to the current key value may also be identified. In addition, at least one of either a displacement characteristic of the object, or a shape characteristic of the object is determined. A probability is determined that indicates the current key value is a particular one or more of the key values in the set.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: December 19, 2006
    Assignee: Canesta, Inc.
    Inventors: Helena Roeber, Ilhami Torunoglu, Abbas Rafii
  • Publication number: 20060176469
    Abstract: TOF system shutter time needed to acquire image data in a time-of-flight (TOF) system that acquires consecutive images is reduced, thus decreasing the time in which relative motion can occur. In one embodiment, pixel detectors are clocked with multi-phase signals and integration of the four signals occurs simultaneously to yield four phase measurements from four pixel detectors within a single shutter time unit. In another embodiment, phase measurement time is reduced by a factor (1/k) by providing super pixels whose collection region is increased by a factor “k” relative to a normal pixel detector. Each super pixel is coupled to k storage units and four-phase sequential signals. Alternatively, each pixel detector can have k collector regions, k storage units, and share common clock circuitry that generates four-phase signals. Various embodiments can reduce the mal-effects of clock signal transients upon signals, and can be dynamically reconfigured as required.
    Type: Application
    Filed: February 8, 2006
    Publication date: August 10, 2006
    Inventors: Patrick O'Connor, Ilhami Torunoglu, Rajeev Nagabhirana
  • Patent number: 6968524
    Abstract: A method and system are disclosed to optimize an integrated circuit layout design by determining possible lengths of layout rows that will reduce the total area of the integrated circuit layout (FIG. 4B). The possible row lengths (401B) are determined and stored in a memory unit as a set of possible optimal row length values. A set of possible optimal row heights corresponding to the determined set of possible rowlengths is determined and the total chip area is iteratively calculated. Optimal values of rowlength and row height are chosen based upon the maximum chip area reduction. Once the optimal row length and height parameters are chosen, transistor devices placed in each row of the integrated circuit layout are folded to achieve the optimal row length and height.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: November 22, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yanbin Jiang, Ilhami Torunoglu, Cyrus Bamji
  • Publication number: 20040136564
    Abstract: A system and method for determining which key value in a set of key values is to be assigned as a current key value as a result an object intersecting a region where a virtual interface is provided. The virtual interface may enable selection of individual key values in the set. The position is determined using a depth sensor that determines a depth of the position in relation to the location of the depth sensor. A set of previous key values that are pertinent to the current key value may also be identified. In addition, at least one of either a displacement characteristic of the object, or a shape characteristic of the object is determined. A probability is determined that indicates the current key value is a particular one or more of the key values in the set.
    Type: Application
    Filed: August 20, 2003
    Publication date: July 15, 2004
    Inventors: Helena Roeber, Ilhami Torunoglu, Abbas Rafii
  • Publication number: 20040010765
    Abstract: A method and system are disclosed to optimize an integrated circuit layout design by determining possible lengths of layout rows that will reduce the total area of the integrated circuit layout (FIG. 4B). The possible row lengths (401B) are determined and stored in a memory unit as a set of possible optimal row length values. A set of possible optimal row heights corresponding to the determined set of possible rowlengths is determined and the total chip area is iteratively calculated. Optimal values of rowlength and row height are chosen based upon the maximum chip area reduction. Once the optimal row length and height parameters are chosen, transistor devices placed in each row of the integrated circuit layout are folded to achieve the optimal row length and height.
    Type: Application
    Filed: May 28, 2003
    Publication date: January 15, 2004
    Inventors: Yanbin Jiang, Ilhami Torunoglu, Cyrus Bamji
  • Publication number: 20030174125
    Abstract: In a sensory input system that detects movement of a user's fingers on an inert work surface, two or more input modes (for instance, keyboard and mouse) are provided within an overlapping or coextensive physical space. Depending on the currently active mode, the invention interprets the finger motions as input according to one of the input modes. Automated and/or manual mode-switching are provided.
    Type: Application
    Filed: February 13, 2003
    Publication date: September 18, 2003
    Inventors: Ilhami Torunoglu, Apurva Desai, Cheng-Feng Sze, Gagan Prakash, Abbas Rafii