Abstract: Apparatuses and methods for branch prediction are provided. Branch prediction circuitry generates prediction with respect to branch instructions of whether those branches will be taken or not-taken. Hypervector generation circuitry assigns an arbitrary hypervector in deterministic dependence on an address of each branch instruction, wherein the hypervectors comprises at least 500 bits. Upon the resolution of a branch a corresponding hypervector is added to a stored taken hypervector or a stored not-taken hypervector in dependence on the resolution of the branch. The branch prediction circuitry generates a prediction for a branch instructions in dependence on a mathematical distance metric of a hypervector generated for that branch instruction from the stored taken hypervector or the not-taken hypervector.

Abstract: Apparatus comprises two or more processing devices each having an associated translation lookaside buffer to store translation data defining address translations between virtual and physical memory addresses, each address translation being associated with a respective virtual address space; and control circuitry to control the transfer of at least a subset of the translation data from the translation lookaside buffer associated with a first processing device to the translation lookaside buffer associated with a second, different, processing device.

Abstract: A branch predictor is provided with a branch state buffer, branch prediction save circuitry responsive to a branch prediction save event associated with a given execution context to save at least a portion of the active branch prediction state associated with the given execution context to a branch state buffer; and branch prediction restore circuitry responsive to a branch prediction restore event associated with the given execution context to restore active branch prediction state based on previously saved branch prediction state stored in the branch state buffer for the given execution context. This is useful for reducing the performance impact of mitigating against speculative side-channel attacks.

Abstract: Apparatus comprises two or more processing devices each having an associated translation lookaside buffer to store translation data defining address translations between virtual and physical memory addresses, each address translation being associated with a respective virtual address space; and control circuitry to control the transfer of at least a subset of the translation data from the translation lookaside buffer associated with a first processing device to the translation lookaside buffer associated with a second, different, processing device.

Abstract: A TAGE branch predictor has, as its fallback predictor, a perceptron predictor. This provides a branch predictor which reduces the penalty of context switches and branch prediction state flushes.

Abstract: A branch predictor is provided with a branch state buffer, branch prediction save circuitry responsive to a branch prediction save event associated with a given execution context to save at least a portion of the active branch prediction state associated with the given execution context to a branch state buffer; and branch prediction restore circuitry responsive to a branch prediction restore event associated with the given execution context to restore active branch prediction state based on previously saved branch prediction state stored in the branch state buffer for the given execution context. This is useful for reducing the performance impact of mitigating against speculative side-channel attacks.

Abstract: A TAGE branch predictor has, as its fallback predictor, a perceptron predictor. This provides a branch predictor which reduces the penalty of context switches and branch prediction state flushes.