Patents by Inventor Ilie Garbacea

Ilie Garbacea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10706825
    Abstract: Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 7, 2020
    Assignee: Apple Inc.
    Inventors: Brijesh Tripathi, Arthur L. Spence, Joshua P. de Cesare, Ilie Garbacea, Guy Cote, Mahesh B. Chappalli, Malcolm D. Gray, Christopher P. Tann
  • Patent number: 10534614
    Abstract: A method of sharing a plurality of registers in a shared register pool among a plurality of microprocessor threads begins with a determination that a first instruction to be executed by a microprocessor in a first microprocessor thread requires a first logical register. Next a determination is made that a second instruction to be executed by the microprocessor in a second microprocessor thread requires a second logical register. A first physical register in the shared register pool is allocated to the first microprocessor thread for execution of the first instruction and the first logical register is mapped to the first physical register. A second physical register in the shared register pool is allocated to the second microprocessor thread for execution of the second instruction. Finally, the second logical register is mapped to the second physical register.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: January 14, 2020
    Assignee: MIPS Tech, LLC
    Inventor: Ilie Garbacea
  • Patent number: 10535287
    Abstract: Systems and methods are provided for improving displayed image quality of an electronic display that includes a display pixel. The electronic display displays a first image frame directly after a second image frame by applying an analog electrical signal to the display pixel. To facilitate display of the first image frame, circuitry receives image data corresponding to the image frame, in which the image data includes a grayscale value that indicates target luminance of the display pixel; determines expected refresh rate of the first image frame based at least in part on actual refresh rate of the second image frame; determines a pixel response correction offset based at least in part on the expected refresh rate of the first image frame; and determines processed image data by applying the pixel response correction offset to the grayscale value, in which the processed image data indicates magnitude of the analog electrical signal.
    Type: Grant
    Filed: September 24, 2016
    Date of Patent: January 14, 2020
    Assignee: Apple Inc.
    Inventors: Chaohao Wang, Lu Zhang, Zhibing Ge, Shih-Chyuan Fan Jiang, Ilie Garbacea, Marc Albrecht, Kingsuk Brahma, Hopil Bae, Paolo Sacchetto, Jie Won Ryu, Sandro H. Pintz, Chengrui Le
  • Patent number: 10410587
    Abstract: Systems and methods for improving displayed image quality of an electronic display including a display pixel that displays an image frame based at least in part on an analog electrical signal supplied to the display pixel are provided. In some embodiments, control circuitry instructs the electronic display to display the image frame based at least in part on an expected charge accumulation in the display pixel determined using a charge accumulation model that describes one or more electric fields expected to be present in the display pixel when displaying the image frame and that provides a display pixel state indicative of expected charge accumulation in the display pixel when the image frame is to be displayed based at least in part on the one or more electric fields.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 10, 2019
    Assignee: Apple Inc.
    Inventors: Ilie Garbacea, Chaohao Wang, Chengrui Le
  • Publication number: 20180090075
    Abstract: Systems and methods for improving displayed image quality of an electronic display including a display pixel that displays an image frame based at least in part on an analog electrical signal supplied to the display pixel are provided. In some embodiments, control circuitry instructs the electronic display to display the image frame based at least in part on an expected charge accumulation in the display pixel determined using a charge accumulation model that describes one or more electric fields expected to be present in the display pixel when displaying the image frame and that provides a display pixel state indicative of expected charge accumulation in the display pixel when the image frame is to be displayed based at least in part on the one or more electric fields.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Inventors: Ilie Garbacea, Chaohao Wang, Chengrui Le
  • Publication number: 20170243548
    Abstract: Systems and methods are provided for improving displayed image quality of an electronic display that includes a display pixel. The electronic display displays a first image frame directly after a second image frame by applying an analog electrical signal to the display pixel. To facilitate display of the first image frame, circuitry receives image data corresponding to the image frame, in which the image data includes a grayscale value that indicates target luminance of the display pixel; determines expected refresh rate of the first image frame based at least in part on actual refresh rate of the second image frame; determines a pixel response correction offset based at least in part on the expected refresh rate of the first image frame; and determines processed image data by applying the pixel response correction offset to the grayscale value, in which the processed image data indicates magnitude of the analog electrical signal.
    Type: Application
    Filed: September 24, 2016
    Publication date: August 24, 2017
    Inventors: Chaohao Wang, Lu Zhang, Zhibing Ge, Shih-Chyuan Fan Jiang, Ilie Garbacea, Marc Albrecht, Kingsuk Brahma, Hopil Bae, Paolo Sacchetto, Jie Won Ryu, Sandro H. Pintz, Chengrui Le
  • Publication number: 20170092236
    Abstract: Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Inventors: Brijesh Tripathi, Arthur L. Spence, Joshua P. de Cesare, Ilie Garbacea, Guy Cote, Mahesh B. Chappalli, Malcolm D. Gray
  • Patent number: 9280513
    Abstract: Processor-to-processor (P-P) and/or broadcast proxies may be designated in a microprocessor matrix comprising a plurality of mesh-interconnected matrix processors when default processor-to-processor or broadcast routing algorithms used by data switches within the matrix to route messages would not deliver the messages to all intended recipients. The broadcast proxies broadcast messages within individual non-overlapping broadcast domains of the matrix. P-to-P and broadcast proxies may be designated as part of a boot-time testing/initialization sequence. Improving system fault tolerance allows improving semiconductor processing yields, which may be of particular significance in relatively large integrated circuits including large numbers of relatively-complex matrix processors.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: March 8, 2016
    Assignee: OVICS
    Inventors: Sorin C. Cismas, Ilie Garbacea
  • Patent number: 8831093
    Abstract: In some embodiments, macroblock-level encoding parameters are assigned to weighted linear combinations of corresponding content-category-level encoding parameters. For example, a macroblock quantization parameter (QP) modulation is set to a weighted linear combination of content category QP modulations. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: September 9, 2014
    Assignee: Geo Semiconductor Inc.
    Inventors: Ilie Garbacea, Lulin Chen, Jose R. Alvarez
  • Publication number: 20140244987
    Abstract: Methods and systems that perform one or more operations on a plurality of elements using a multiple data processing element processor are provided. An input vector comprising a plurality of elements is received by a processor. The processor determines if performing a first operation on a first element will cause an exception and if so, writes an indication of the exception caused by the first operation to a first portion of an output vector stored in an output register. A second operation can be performed on a second element with the result of the second operation being written to a second portion of the output vector stored in the output register.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicant: MIPS Technologies, Inc.
    Inventors: Ilie GARBACEA, James ROBINSON
  • Publication number: 20140244977
    Abstract: A method of sharing a plurality of registers in a register pool among a plurality of microprocessor threads begins by allocating a first set of registers in the register pool to a first thread, the first thread executing a first instruction using the first set of registers in the register pool. The first thread is descheduled without saving values stored in the first set of registers. A second thread is scheduled to execute a second instruction using registers allocated in the register pool. Finally, the first thread is rescheduled, the first thread reusing the allocated first set of registers.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicants: MIPS Technologies, Inc.
    Inventor: Ilie GARBACEA
  • Patent number: 8640129
    Abstract: According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substrates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: January 28, 2014
    Assignee: Geo Semiconductor Inc.
    Inventors: Sorin C. Cismas, Ilie Garbacea, Kristan J. Monsen
  • Publication number: 20130332703
    Abstract: A method of sharing a plurality of registers in a shared register pool among a plurality of microprocessor threads begins with a determination that a first instruction to be executed by a microprocessor in a first microprocessor thread requires a first logical register. Next a determination is made that a second instruction to be executed by the microprocessor in a second microprocessor thread requires a second logical register. A first physical register in the shared register pool is allocated to the first microprocessor thread for execution of the first instruction and the first logical register is mapped to the first physical register. A second physical register in the shared register pool is allocated to the second microprocessor thread for execution of the second instruction. Finally, the second logical register is mapped to the second physical register.
    Type: Application
    Filed: June 8, 2012
    Publication date: December 12, 2013
    Applicant: MIPS Technologies, Inc.
    Inventor: Ilie GARBACEA
  • Publication number: 20130188689
    Abstract: In some embodiments, macroblock-level encoding parameters are assigned to weighted linear combinations of corresponding content-category-level encoding parameters. For example, a macroblock quantization parameter (QP) modulation is set to a weighted linear combination of content category QP modulations. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition.
    Type: Application
    Filed: April 2, 2012
    Publication date: July 25, 2013
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Ilie Garbacea, Lulin Chen, Jose R. Alvarez
  • Publication number: 20130159667
    Abstract: A computer has a memory adapted to store a first plurality of instructions encoded with a first vector size and a second plurality of instructions encoded with a second vector size. An execution unit executes the first plurality of instructions and the second plurality of instructions by processing vector units in a uniform manner regardless of vector size.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: MIPS TECHNOLOGIES, INC.
    Inventor: Ilie Garbacea
  • Patent number: 8327114
    Abstract: In some embodiments, processor-to-processor and/or broadcast proxies are designated in a microprocessor matrix comprising a plurality of mesh-interconnected matrix processors when default processor-to-processor or broadcast routing algorithms used by data switches within the matrix to route messages would not deliver the messages to all intended recipients. The broadcast proxies broadcast messages within individual non-overlapping broadcast domains of the matrix. P-to-P and broadcast proxies may be designated as part of a boot-time testing/initialization sequence. Improving system fault tolerance allows improving semiconductor processing yields, which may be of particular significance in relatively large integrated circuits including large numbers of relatively-complex matrix processors.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: December 4, 2012
    Assignee: Ovics
    Inventors: Sorin C Cismas, Ilie Garbacea
  • Patent number: 8149909
    Abstract: In some embodiments, macroblock-level encoding parameters are assigned to weighted Linear combinations of corresponding content-category-level encoding parameters. A macroblock quantization parameter (QP) modulation is set to a weighted linear combination of content category QP modulations. Content categories may identify potentially overlapping content types. The combination weights may be similarity measures describing macroblock similarities to content categories. A macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Content-category-level statistics are generated by combining block-level statistics.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: April 3, 2012
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ilie Garbacea, Lulin Chen, Jose R. Alvarez
  • Patent number: 8145880
    Abstract: According to some embodiments, an integrated circuit comprises a microprocessor matrix of mesh-interconnected matrix processors. Each processor comprises a data switch including a data switch link register and matrix routing logic. The data switch link register includes one or more matrix link-enable register fields specifying a link enable status (e.g. a message-independent, p-to-p, and/or broadcast link enable status) for each inter-processor matrix link of the processor. The matrix routing logic routes inter-processor messages according to the matrix link-enable register field(s). A particular link may be selected by a current matrix processor by selecting an ordered list of matrix links according to a relationship between ?H and ?V, and choosing the first enabled link in the selected list for routing.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: March 27, 2012
    Assignee: Ovics
    Inventors: Sorin C Cismas, Ilie Garbacea
  • Patent number: 8131975
    Abstract: In some embodiments, an integrated circuit comprises a microprocessor matrix including a plurality of mesh-interconnected matrix processors, wherein each matrix processor comprises a data switch configured to direct inter-processor communications within the matrix, and a mapping unit configured to generate a data switch functionality map for a plurality of data switches in the microprocessor matrix. The data switch functionality map is generated by sending a first message through the matrix, and, setting a first functionality status designation for the first data switch in the data switch functionality map upon receiving a reply to the first message from a first data switch through the matrix.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: March 6, 2012
    Assignee: Ovics
    Inventors: Sorin C Cismas, Ilie Garbacea
  • Patent number: 8126283
    Abstract: In some embodiments, content-category-level encoding statistical indicators (statistics) are assigned to weighted linear combinations of corresponding macroblock-level statistics. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A given macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Macroblock-level encoding parameters are generated by combining content-category-level parameters.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: February 28, 2012
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ilie Garbacea, Lulin Chen, Jose R. Alvarez