Patents by Inventor Iliya G. Zamek

Iliya G. Zamek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9038007
    Abstract: A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: May 19, 2015
    Assignee: Altera Corporation
    Inventors: Peter Boyle, Iliya G. Zamek
  • Publication number: 20120198410
    Abstract: A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.
    Type: Application
    Filed: February 3, 2012
    Publication date: August 2, 2012
    Inventors: Peter Boyle, Iliya G. Zamek
  • Patent number: 8132137
    Abstract: A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. In one embodiment, the timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, the power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: March 6, 2012
    Assignee: Altera Corporation
    Inventors: Peter Boyle, Iliya G. Zamek
  • Patent number: 7962870
    Abstract: A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then converted to a frequency domain current waveform. With the frequency domain waveform, one skilled in the art can then identify a location and an amount of decoupling capacitors for a printed circuit board housing the circuit design based on the frequency domain current waveform. A computing system configured to perform the method is also provided.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: June 14, 2011
    Assignee: Altera Corporation
    Inventors: Peter Boyle, Iliya G. Zamek, Zhe Li, Shishuang Sun, Bozidar Krsnik, James L. Drewniak, Xiaohe Chen, Sandeep Kamalakar Reddy Chandra
  • Patent number: 7683659
    Abstract: Integrated circuits contain core logic that is powered using a power supply signal. The core logic contains simultaneously switching circuitry. The simultaneously switching circuitry contributes to noise on the power supply signal. Balancing circuitry may be provided on the integrated circuit to compensate for the simultaneously switching circuitry in the core logic. The balancing circuitry may receive an input signal that is out of phase with respect to the input to the core logic. As the balancing circuitry switches out of phase with the simultaneously switching circuitry of the core logic, the noise contribution from the core logic is compensated and power supply noise on the power supply signal is minimized.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: March 23, 2010
    Assignee: Altera Corporation
    Inventors: Iliya G. Zamek, Nafira Daud, Peter Boyle, Eugene V. Gomez
  • Patent number: 7669151
    Abstract: Computer-aided design tools analyze a custom logic design for a programmable logic device integrated circuit. The tools identify distinct clock domains in the design. The tools also identify which of the clock domains are synchronous. The tools examine the synchronous clock domains to determine which of the clock domains have required fixed phase relationships. Clocks for clock domains that do not have required fixed relationships can be adjusted in phase to minimize power supply simultaneous switching noise. Noise may be minimized by making clock phase adjustments using a programmable phase-locked loop circuit.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: February 23, 2010
    Assignee: Altera Corporation
    Inventors: Peter Boyle, Iliya G. Zamek, Zhe Li, Lawrence David Smith
  • Publication number: 20080288898
    Abstract: A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then converted to a frequency domain current waveform. With the frequency domain waveform, one skilled in the art can then identify a location and an amount of decoupling capacitors for a printed circuit board housing the circuit design based on the frequency domain current waveform. A computing system configured to perform the method is also provided.
    Type: Application
    Filed: May 6, 2008
    Publication date: November 20, 2008
    Inventors: Peter Boyle, Iliya G. Zamek, Zhe Li, Shishuang Sun, Bozidar Krsnik, James L. Drewniak
  • Patent number: 7454301
    Abstract: A jitter calculator engine that includes a core effects module, an input/output (I/O) module, and a phase lock loop (PLL) module is provided. The core effects module estimates core jitter caused by noise effects impacting a core clock network. The I/O module estimates I/O input pin switching effects on a clock network input signal. In one embodiment, the I/O module identifies a relative frequency of switching by I/O pins in the circuit design. The PLL module estimates an effect of a PLL on a signal delivered to the PLL from an I/O pin. The PLL module accounts for I/O input pin switching effects and core jitter. The jitter calculator engine may be in communication with a database and the different designs evaluated may be stored in the database so that the database becomes a repository for the different designs and may provide useful information for future designs.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: November 18, 2008
    Assignee: Altera Corporation
    Inventors: Nafira Daud, Iliya G. Zamek, Peter Boyle