Abstract: Provided are a carbon dioxide absorbing composition including an ionic material containing a spiro ammonium cation and a method of separating carbon dioxide using the same, and the carbon dioxide absorbing composition of the present disclosure has high thermal and chemical stability and excellent carbon dioxide absorption effect. In addition, the method of separating carbon dioxide using the carbon dioxide absorbing composition is very effective for desorption of carbon dioxide, and is a very economical method since it allows repeated use of the carbon dioxide absorbing composition.

Abstract: Provided are a carbon dioxide absorbing composition comprising an ionic material comprising a cyclic ammonium cation and a method of separating carbon dioxide using the same, and the carbon dioxide absorbing composition of the present disclosure has high thermal and chemical stability and excellent carbon dioxide absorption effect. In addition, the method of separating carbon dioxide using the carbon dioxide absorbing composition is very effective for desorption of carbon dioxide, and is a very economical method since it allows repeated use of the carbon dioxide absorbing composition.

Abstract: Some example embodiments relate to a super resolution scanning electron microscope (SEM) image implementing device and/or a method thereof. Provided a super resolution scanning electron microscope (SEM) image implementing device comprising a processor configured to crop a low resolution SEM image to generate a first cropped image and a second cropped image, to upscale the first cropped image and the second cropped image to generate a first upscaled image and a second upscaled image, and to cancel noise from the first upscaled image and the second upscaled image to generate a first noise canceled image and a second noise canceled image.

Abstract: A memory package includes a multi-level package substrate, a first memory chip, a second memory chip, a first band pass filter and a second band pass filter. The multi-level package substrate includes a plurality of wiring layers and a plurality of insulating layers alternately stacked on one another. The first memory chip is on the multi-level package substrate, and includes a plurality of first memory cells and a first receiver. The second memory chip is on the first memory chip, and includes a plurality of second memory cells and a second receiver. The first band pass filter is in the multi-level package substrate, is connected to the first receiver, and passes a first data signal within a first frequency band. The second band pass filter is in the multi-level package substrate, is connected to the second receiver, and passes a second data signal within the first frequency band.

Abstract: A memory package includes a multi-level package substrate, a first memory chip, a second memory chip, a first band pass filter and a second band pass filter. The multi-level package substrate includes a plurality of wiring layers and a plurality of insulating layers alternately stacked on one another. The first memory chip is on the multi-level package substrate, and includes a plurality of first memory cells and a first receiver. The second memory chip is on the first memory chip, and includes a plurality of second memory cells and a second receiver. The first band pass filter is in the multi-level package substrate, is connected to the first receiver, and passes a first data signal within a first frequency band. The second band pass filter is in the multi-level package substrate, is connected to the second receiver, and passes a second data signal within the first frequency band.

Abstract: A semiconductor package includes a printed circuit board, a resistor circuit, and first and second semiconductor chips. First and second pads are on a first surface of the printed circuit board, and external connection terminal is on a second surface of the printed circuit board. The resistor circuit has a first connection terminal connected to the first pad and a second connection terminal connected to the second pad. The first semiconductor chip is connected to the first pad and the second semiconductor chip is stacked on the first semiconductor chip and connected to the second pad. The printed circuit board includes a signal transfer line connecting a branch in the printed circuit board to the external connection terminal. A first transfer line connects the branch to the first pad. A second transfer line connects the branch to the second pad.

Abstract: A semiconductor package includes a printed circuit board, a resistor circuit, and first and second semiconductor chips. First and second pads are on a first surface of the printed circuit board, and external connection terminal is on a second surface of the printed circuit board. The resistor circuit has a first connection terminal connected to the first pad and a second connection terminal connected to the second pad. The first semiconductor chip is connected to the first pad and the second semiconductor chip is stacked on the first semiconductor chip and connected to the second pad. The printed circuit board includes a signal transfer line connecting a branch in the printed circuit board to the external connection terminal. A first transfer line connects the branch to the first pad. A second transfer line connects the branch to the second pad.

Abstract: A semiconductor device includes a first set of pads disposed at a first vertical level on a substrate, a first interconnection layer formed at a second vertical level higher than the first vertical level on the substrate, a second interconnection layer formed at a third vertical level higher than the second vertical level on the substrate, capacitive elements included in either the first or the second interconnection layer, and a second set of pads disposed at a fourth vertical level higher than the third vertical level on the substrate. A first capacitive element of the capacitive elements is connected between a first portion and a second portion of the first interconnection layer or a first capacitive element of the capacitive elements is connected between a third portion and a fourth portion of the second interconnection layer.

Abstract: A refresh control method of a semiconductor package, comprising: providing a semiconductor package including a first semiconductor chip and a second semiconductor chip; monitoring a temperature of each of a plurality of sensing areas of the first semiconductor chip when the first semiconductor chip operates; identifying at least one memory bank of the second semiconductor chip corresponding to an area having a lower temperature among the sensing areas; controlling the second semiconductor chip to transfer data to the identified memory bank from another memory bank of the second semiconductor chip; and controlling a refresh operation of the second semiconductor chip such that a period of a refresh operation on the identified memory bank is greater than that of a period of a refresh operation on the other memory bank.

Abstract: A refresh control method of a semiconductor package, comprising: providing a semiconductor package including a first semiconductor chip and a second semiconductor chip; monitoring a temperature of each of a plurality of sensing areas of the first semiconductor chip when the first semiconductor chip operates; identifying at least one memory bank of the second semiconductor chip corresponding to an area having a lower temperature among the sensing areas; controlling the second semiconductor chip to transfer data to the identified memory bank from another memory bank of the second semiconductor chip; and controlling a refresh operation of the second semiconductor chip such that a period of a refresh operation on the identified memory bank is greater than that of a period of a refresh operation on the other memory bank.