Abstract: The present invention discloses a filter for removing noise, which includes: a lower magnetic body; primary and secondary patterns spirally provided on the lower magnetic body in parallel to each other; an insulating layer for covering the primary and secondary patterns; and an upper magnetic body provided on the insulating layer, wherein the primary and secondary patterns are formed to have a ratio of vertical thickness (T) to horizontal width (W) of 0.27?T/W?2.4. According to the present invention, it is possible to improve performance and capacity by implementing high common-mode impedance in the same frequency and reduce manufacturing costs by simplifying structures and processes.

Abstract: The present invention discloses a filter for removing noise, which includes: a lower magnetic body; primary and secondary patterns spirally provided on the lower magnetic body in parallel to each other; an insulating layer for covering the primary and secondary patterns; and an upper magnetic body provided on the insulating layer, wherein the primary and secondary patterns are formed to have a ratio of vertical thickness (T) to horizontal width (W) of 0.27?T/W?2.4. According to the present invention, it is possible to improve performance and capacity by implementing high common-mode impedance in the same frequency and reduce manufacturing costs by simplifying structures and processes.

Abstract: There is provided an electric double layer capacitor including: an exterior case having a housing space provided therein and formed of insulating resin; first and second external terminals buried in the exterior case, each having a first surface exposed to the housing space and a second surface exposed to an outside of the exterior case; and a chip-type electric double layer capacitor cell disposed in the housing space and electrically connected to the first surface. The chip-type electric double layer capacitor cell includes first and second electrodes facing each other and having electricity of opposite polarities applied thereto, at least one induction electrode layer disposed between the first and second electrodes and having no electricity applied thereto, and first and second separators disposed between the first electrode and the induction electrode layer and between the second electrode and the induction electrode layer, respectively.

Abstract: There are provided a modeling circuit of a high-frequency device capable of providing a more accurate modeling circuit having a higher-order resonance by dividedly modeling an overlap zone and a non-overlap zone of the high-frequency device, and a modeling method thereof.

Abstract: The present invention provides a chip type electric double layer capacitor including: a lower case having an internal space of which an upper surface is opened and an external terminal of which portions exposed to a bottom of the internal space and the outside are connected to each other; an electric double layer capacitor cell disposed in the internal space of the lower case to be electrically connected to the portion of the external terminal, which is exposed to the bottom of the internal space; and an upper cap mounted on the lower case to cover the internal space, and a method for manufacturing the same.

Abstract: There is provided an electric double layer capacitor including: an exterior case having a housing space provided therein and formed of insulating resin; first and second external terminals buried in the exterior case, each having a first surface exposed to the housing space and a second surface exposed to an outside of the exterior case; and a chip-type electric double layer capacitor cell disposed in the housing space and electrically connected to the first surface. The chip-type electric double layer capacitor cell includes first and second electrodes facing each other and having electricity of opposite polarities applied thereto, at least one induction electrode layer disposed between the first and second electrodes and having no electricity applied thereto, and first and second separators disposed between the first electrode and the induction electrode layer and between the second electrode and the induction electrode layer, respectively.

Abstract: The present invention provides a chip type electric double layer capacitor including: a lower case having an internal space of which an upper surface is opened and an external terminal of which portions exposed to a bottom of the internal space and the outside are connected to each other; an electric double layer capacitor cell disposed in the internal space of the lower case to be electrically connected to the portion of the external terminal, which is exposed to the bottom of the internal space; and an upper cap mounted on the lower case to cover the internal space, and a method for manufacturing the same.

Abstract: There are provided a modeling circuit of a high-frequency device capable of providing a more accurate modeling circuit having a higher-order resonance by dividedly modeling an overlap zone and a non-overlap zone of the high-frequency device, and a modeling method thereof.