Patents by Inventor Illaria Katia Marianna Pellicano

Illaria Katia Marianna Pellicano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
    Patent number: 10672645
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 2, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Illaria Katia Marianna Pellicano
  • METHOD OF MANUFACTURING HIGH RESISTIVITY SOI WAFERS WITH CHARGE TRAPPING LAYERS BASED ON TERMINATED SI DEPOSITION
    Publication number: 20190013235
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
    Type: Application
    Filed: August 21, 2018
    Publication date: January 10, 2019
    Inventors: Igor Peidous, Illaria Katia Marianna Pellicano
  • Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
    Patent number: 10083855
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: September 25, 2018
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Illaria Katia Marianna Pellicano
  • METHOD OF MANUFACTURING HIGH RESISTIVITY SOI WAFERS WITH CHARGE TRAPPING LAYERS BASED ON TERMINATED SI DEPOSITION
    Publication number: 20170365506
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
    Type: Application
    Filed: August 11, 2017
    Publication date: December 21, 2017
    Inventors: Igor Peidous, Illaria Katia Marianna Pellicano
  • Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
    Patent number: 9768056
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: September 19, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Igor Peidous, Illaria Katia Marianna Pellicano
  • METHOD OF MANUFACTURING HIGH RESISTIVITY SOI WAFERS WITH CHARGE TRAPPING LAYERS BASED ON TERMINATED SI DEPOSITION
    Publication number: 20150115480
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 30, 2015
    Inventors: Igor Peidous, Illaria Katia Marianna Pellicano