Abstract: Embodiments of apparatus, computer-implemented methods, computing devices, systems, and computer-readable media (transitory and non-transitory) are described herein for scheduling a plurality of tasks among a plurality of processor cores. A first processor core of a plurality of processor cores of a computing device may be transitioned to a shielded state, in which no new tasks are to be assigned to the first processor core and tasks already assigned to the first processor core are executed to completion, in response to a determination that a criterion has been met. In various embodiments, the criterion may be based on a condition of the computing device, such as power available to the computing device or a temperature associated with the computing device. In various embodiments, the first processor core may transition to a reduced-power state after the tasks already assigned to the first processor core execute completion.

Abstract: Embodiments of apparatus, computer-implemented methods, computing devices, systems, and computer-readable media (transitory and non-transitory) are described herein for scheduling a plurality of tasks among a plurality of processor cores. A first processor core of a plurality of processor cores of a computing device may be transitioned to a shielded state, in which no new tasks are to be assigned to the first processor core and tasks already assigned to the first processor core are executed to completion, in response to a determination that a criterion has been met. In various embodiments, the criterion may be based on a condition of the computing device, such as power available to the computing device or a temperature associated with the computing device. In various embodiments, the first processor core may transition to a reduced-power state after the tasks already assigned to the first processor core execute completion.