Abstract: A delay equalization circuit for minimizing the static phase error in a PLL is provided. The delay equalization circuit includes an external clock signal variable delay path, and an element for creating a pulse with a width proportional to the delay of the external clock signal variable delay path. The delay equalization circuit also includes a delay path in the feedback loop, and second element for creating a second pulse in proportion to the delay of the internal delay path. Finally, the circuit contains a comparison device. The comparison device compares the first and second pulses. The comparison device outputs a difference signal in proportion to the difference in the external and internal path delays. That difference signal is fed back and used to control the external path delay such that the external delay is driven to be substantially equal to the internal delay, minimizing the static phase error of the PLL device.

Abstract: A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.

Abstract: An integrated current reference circuit provides a current output with a predetermined temperature coefficient, suitably zero, to provide constant current over temperature variations. The circuit is formed of only Field Effect Transistors (FETs), allowing the circuit to be implemented using conventional CMOS fabrication techniques. A current mirror provides a reference current in both branches of the circuit. The output of the current mirror is coupled to a circuit providing an imbalance in resistance between the two branches, and an offsetting imbalance in voltages between the two branches, resulting in a reference current that has a predetermined temperature coefficient. An output current is provided which is proportional to the reference current and thus has the same temperature coefficient as the reference current.

Abstract: A phase locked loop circuit is provided which includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which do not have "dead zones". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has a voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is also provided which reduces jitter in the current controlled oscillator output in the locked phase.

Abstract: An improved configuration of a capacitor formed with FET technology and a resistor and/or conductor is provided. In this configuration a capacitor is formed in which the diffusion zone of the substrate is used as one plate of the capacitor and what would normally be the gate electrode of an FET is used as the other plate of the capacitor, with the two plates being separated by a conventional thin dielectric gate oxide layer. An insulator, such as silicon dioxide overlays the gate electrode, and electrical connections to the gate electrode and diffusion zone are made through the insulator to allow the two plates of the capacitor to be connected to various devices or components as required. The top surface of this insulation layer is also used to form metal resistors. Depending on the value of required resistance, a second insulating layer may be used and a second level of metal used to connect segments of the resistors formed on the first layer of metal to form a longer resistor.

Abstract: A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase.

Abstract: A phase-controlled loop system having a charge pump circuit including a current mismatch measurement circuit and a current compensation circuit for equalizing the amplitude of positive current pulses and the amplitude of negative current pulses output when the phase-controlled loop system is in phase-locked condition. The current mismatch measurement circuit includes duplicate complementary current sources with characteristics and biasing substantially identical to that of the primary current sources providing the positive current and the negative current to the output node of the charge pump circuit. At the common connected node between the duplicate complementary current sources an error current is produced having an amplitude equal to the difference between the amplitude of the positive current pulses and the amplitude of the negative current pulses to the output node.

Abstract: A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase.

Abstract: A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase.

Abstract: A system and method is provided for estimating the bit error rate of a data signal which has been reconstructed from a received data signal. The system comprises (i) logic for determining timing degradation and amplitude degradation of the received data signal; (ii) an actual bit error rate calculator for calculating the actual bit error rate of the reconstructed data signal; (iii) an instantaneous bit error rate calculator for estimating a bit error rate of the reconstructed signal using the timing degradation and the amplitude degradation; (iv) a first integrator for integrating the estimated bit error rate; (v) a comparator for comparing the integrated estimated bit error rate with the actual bit error rate and outputting an error signal which modifies the estimated bit error rate; and (vi) a second integrator for integrating the estimated bit error rate. The time constant associated with the second integrator is shorter than the time constant associated with the first integrator.

Abstract: Clock extraction and data regeneration logic is provided for a multiple rate digital data communications system such as a local area network (LAN). The logic is implemented in adapters which connect stations in the LAN to other stations in the LAN via transmission media such as wire or fiber optic cable. The clock extraction and data regeneration logic is adapted to quickly recognize the speed at which the token ring is operating, thereby preventing a station on the ring from sending data onto the ring at a rate which does not match the operating frequency of the ring. The logic also performs, at multiple speeds of operation, clock extraction and data reconstruction of a signal received from another station in the ring.

Abstract: A digital phase lock loop is provided, comprising a digital voltage controlled oscillator, a phase detector, and an up/down counter. The digital voltage controlled oscillator is responsive to a first set of control signals received from the up/down counter to provide an output signal. The phase detector receives and compares the frequency of the output signal with the frequency of a reference signal and, based on the comparison, outputs to the up/down counter a second control signal which determines the status of the first set of control signals. The digital voltage controlled oscillator comprises (i) an array of delay elements and (ii) a decoder for receiving the first set of the control signals from the up/down counter and for selectively activating one or more of the delay elements in response thereto. The decoder provides a separate output line for each of the delay elements which is to be selectively activated.

Abstract: An adaptive regeneration system is provided for reconstructing a signal received in the form of a multi-level composite data and clock signal which has been degraded with respect to amplitude and timing. The system includes a local clock circuit for outputting a plurality of phase-delayed local clock signals, and a clock recovery circuit for receiving the received multi-level signal and the plurality of phase-delayed clock signals and extracting a phase-delayed local clock signal which most accurately represents the phase shift between the received multi-level signal and the local clock signal. A threshold level selection circuit receives the extracted phase-delayed local clock signal and the received multi-level signal and outputs in real time a data amplitude reading and a plurality of multi-level threshold levels corresponding to the amplitude levels of the received multi-level signal.

Abstract: An adaptive equalization and regeneration system is provided for accurately reconstructing a received data pulse train which has been degraded with respect to amplitude and instantaneous frequency. The system comprises an equalizer which responds to a control signal to provide a variable gain function for the received signal and output an equalized signal, digital phase lock logic for receiving and extracting timing information from the equalized signal, a regenerator for matching the timing information with the equalized signal to reconstruct the received data in its originally transmitted form, and control circuitry for providing the control signal to the equalizer. The control signal adjusts the slope of the equalizer gain function so as to minimize amplitude and instantaneous frequency degradation at the equalizer output. The system includes a mechanism to detect and calculate total signal degradation at the equalizer output.

Abstract: A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.

Abstract: A phase lock logic system is provided for (i) determining differences in phase and frequency of a received composite clock and data signal with respect to a local clock signal and (ii) providing control signals to enable accurate sampling and reconstruction of the received data. The system includes a delay element which outputs a plurality of phase-delayed signals each being incrementally shifted in phase from the local clock signal. A sorting circuit receives the phase-delayed local clock signals and the incoming composite signal, defines a number of time intervals in each cycle of the local clock signal equal to the number of phase-delayed local clock signals, and sorts positive and negative going transitions in the received composite signal into the defined time intervals. Counters indicate the number of transitions occurring during a selected time interval.

Abstract: A digital data link performance monitor technique for communication systems and information and data processing systems is disclosed. The technique is based on the integration and analysis of a plurality of sorted data edge transitions of a serial data stream received over the digital data link. The number of data edge sorts to each of n time intervals definitive of the edge histogram is compared with a predetermined threshold level and a monitor signal is generated with each comparison. The combination of monitor signals is then analyzed to determine the amount of data timing jitter, and therefore the quality of the link. Corresponding methods and circuits are described.

Abstract: Data edge phase sorting circuits for communication systems and information and data processing systems employing digital phase locked logic circuits. The sorting circuits phase sort edge transitions of a serial data stream relative to a local clock signal. The local clock signal is coupled to a delay line having a plurality of serially connected delay elements, each of which outputs a delay clock of different phase. The sorting circuit includes an extraction circuit coupled to receive the serial data stream for detecting edge transitions in the serial stream and outputting a pulse of predefined duration in response to each detected transition. Coupled to the extraction circuit output is a non-sequential logic circuit, which is also coupled to the local clock through the delay line. The non-sequential logic circuit combines the outputted extraction circuit pulse and the plurality of delay clocks for sorting the pulse relative to the delay clocks.

Abstract: A digital integrating clock extraction technique for communication systems and information and data processing systems having high jitter and/or noise is disclosed. The technique is based on the integration and periodic analysis of a plurality of sorted data edge transitions of a received serial data stream. A retiming clock phase is selected from a plurality of locally generated clock signals of different phase. The retiming clock selection is preferably reevaluated after N data edge transition sorts. The resultant data edge histogram can be cumulative of all sorted transitions or merely cumulative of the last N sorted transitions. Corresponding methods and apparatus are described.

Abstract: A substantially simultaneous digital data regeneration and deserialization technique for communication systems and information and data processing systems is disclosed. A digital phase lock logic circuit (DPLL) receives the serial stream of clock and data bits at its input and outputs a plurality of clock signals with different phase. A plurality of latches are coupled to receive a respective one of the clock output signals from the DPLL. Each latch receives the serial stream of clock and data bits through a second input such that the latches are sequentially set by substantially simultaneously received clock and data information at the two inputs and the serial data bits within the stream appear as parallel data bits at the latch outputs. Enhanced versions of this circuit are also described, along with an alternate embodiment which uses an analog phase locked loop circuit.