Abstract: A computer controlled odor mixing and dispensing system has an linear array of odorant containers arranged in an annular member. Each container is provided with a computer controlled metering delivery device which dispenses the odorant onto a rotating absorptive porus member. An air handling system forces air through the rotating member which mixes the odors deposited thereon and delivers the mixed odors to a user.

Abstract: A phase-lock indicator circuit is disclosed that compares first and second clock signals and indicates when the signals are in-phase. The circuit includes a phase-only detector which is immune to frequency differences. The clock signals are compared by first extracting their leading edges and generating a first pulse signal when the leading edges occur simultaneously. Then, when a consecutive number of first pulse signals has occurred, a second pulse signal is generated, which in turn produces a lock indication signal, indicating that the first clock signal is in-phase with the second clock signal, regardless of whether or not the frequencies of the clock signals are equal. The lock circuit can be used in any PLL circuit regardless of the specific Phase Detector used. The circuit can also be used in any application or circuit where two clocks need to be tracked. In addition, the phase-lock detector includes a loss of input clock feature that indicates if the input clock is lost.

Abstract: A built-in system and method is provided that measures Phase Lock Loop (PLL) output clock error. An edge sorting circuit is utilized to measure jitter between corresponding transition edges of a measured clock and a reference clock, and then stores the value in an N bit word. A decoder circuit reads in the value and increments a corresponding counter. A state machine then reads the counters, processes the information and outputs one or more PLL clock error values.

Abstract: A frequency-lock indicator circuit is disclosed that compares first and second clock signals and indicates when the signals have the same frequencies for a consecutive number of times. The circuit includes a Frequency-Only Detector (FOD) which is immune to phase differences. The frequencies of the clock signals are compared through counters that will reset each other if a consecutive number of frequencies from the clock signals do not occur at the same time. Then, when a consecutive number of equal frequencies has occurred, a first pulse signal is generated, which in turn produces a lock indication signal, indicating that the first clock signal has the same frequency as the second clock signal, regardless of whether or not the phases of the clock signals are equal. The lock indicator circuit can be used in any PLL circuit regardless of the specific Frequency/Phase Detector used. The circuit can also be used in any application or circuit where two clocks need to be tracked.