Abstract: Learning-based color correction (e.g., auto while balance (AWB)) procedures may be trained based on datasets from different sensors using a pre-processing procedure. Each input pixel may be converted into a sensor-independent representation through multiplication by a sensor-specific color conversion function (e.g., a 3×3 matrix). The sensor-specific color conversion function may be obtained based on a sensor type. For example, the sensor-specific color conversion function, such as a 3×3 matrix, may be obtained by a corresponding sensor calibration procedure performed using laboratory images of a color checker chart subject to standard illuminants. Parameters of the sensor-specific color conversion function may be optimized in a chromaticity space. For instance, a sensor-specific 3×3 matrix for color conversion may be optimized using a distance in the chromaticity space between calibration data (e.g., calibration configurations) and sensor-independent targets (e.g.

Abstract: Learning-based color correction (e.g., auto while balance (AWB)) procedures may be trained based on datasets from different sensors using a pre-processing procedure. Each input pixel may be converted into a sensor-independent representation through multiplication by a sensor-specific color conversion function (e.g., a 3×3 matrix). The sensor-specific color conversion function may be obtained based on a sensor type. For example, the sensor-specific color conversion function, such as a 3×3 matrix, may be obtained by a corresponding sensor calibration procedure performed using laboratory images of a color checker chart subject to standard illuminants. Parameters of the sensor-specific color conversion function may be optimized in a chromaticity space. For instance, a sensor-specific 3×3 matrix for color conversion may be optimized using a distance in the chromaticity space between calibration data (e.g., calibration configurations) and sensor-independent targets (e.g.

Abstract: Learning-based color correction (e.g., auto while balance (AWB)) procedures may be trained based on datasets from different sensors using a pre-processing procedure. Each input pixel may be converted into a sensor-independent representation through multiplication by a sensor-specific color conversion function (e.g., a 3×3 matrix). The sensor-specific color conversion function (e.g., the 3×3 matrix) may be obtained based on a sensor type. For example, the sensor-specific color conversion function, such as a 3×3 matrix, may be obtained by a corresponding sensor calibration procedure performed using laboratory images of a color checker chart subject to standard illuminants. Parameters of the sensor-specific color conversion function may be optimized in a chromaticity space. For instance, a sensor-specific 3×3 matrix for color conversion may be optimized using a distance in the chromaticity space between calibration data (e.g., calibration configurations) and sensor-independent targets (e.g.

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

Abstract: In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Abstract: In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.