Patents by Inventor Ilya Sharapov

Ilya Sharapov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10521002
    Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: December 31, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jonathan M. Eastep, Rohit Banerjee, Richard J. Greco, Ilya Sharapov, David N. Lombard, Hari K. Nagpal
  • Patent number: 10466754
    Abstract: Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Jonathan M. Eastep, Ilya Sharapov, Richard J. Greco, Steve S. Sylvester, David N. Lombard
  • Patent number: 9971391
    Abstract: A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Devadatta Bodas, Meenakshi Arunachalam, Ilya Sharapov, Charles R. Yount, Scott B. Huck, Ramakrishna Huggahalli, Justin J. Song, Brian J. Griffith, Muralidhar Rajappa, Lingdan (Linda) Zeng
  • Publication number: 20180059768
    Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.
    Type: Application
    Filed: October 19, 2017
    Publication date: March 1, 2018
    Applicant: INTEL CORPORATION
    Inventors: Jonathan M. Eastep, Rohit Banerjee, Richard J. Greco, Ilya Sharapov, David N. Lombard, Hari K. Nagpal
  • Patent number: 9811143
    Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: November 7, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jonathan M. Eastep, Rohit Banerjee, Richard J. Greco, Ilya Sharapov, David N. Lombard, Hari K. Nagpal
  • Publication number: 20170185132
    Abstract: A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 29, 2017
    Inventors: Devadatta Bodas, Meenakshi Arunachalam, Ilya Sharapov, Charles R. Yount, Scott B. Huck, Ramakrishna Huggahalli, Justin J. Song, Brian J. Griffith, Muralidhar Rajappa, Lingdan (Linda) Zeng
  • Patent number: 9575270
    Abstract: Embodiments of a system that includes an array of chip modules (CMs) is described. In this system, a given CM in the array includes a semiconductor die that is configured to communicate data signals with one or more adjacent CMs through electromagnetic proximity communication using proximity connectors. Note that the proximity connectors are proximate to a surface of the semiconductor die. Moreover, the given CM is configured to communicate optical signals with other CMs through an optical signal path using optical communication, and the optical signals are encoded using wavelength-division multiplexing (WDM).
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: February 21, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Ilya A. Sharapov, Ashok V. Krishnamoorthy, John E. Cunningham, Xuehze Zheng, Brian W. O'Krafka, Ronald Ho
  • Patent number: 9477533
    Abstract: Systems and methods may provide a set of cores capable of parallel execution of threads. Each of the cores may run code that is provided with a progress meter that calculates the amount of work remaining to be performed on threads as they run on their respective cores. The data may be collected continuously, and may be used to alter the frequency, speed or other operating characteristic of the cores as well as groups of cores. The progress meters may be annotated into existing code.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Jonathan M. Eastep, Ilya Sharapov, Rob F. Van Der Wijngaart, Richard J. Greco, Steve S. Sylvester, David N. Lombard
  • Publication number: 20160188380
    Abstract: Systems and methods may provide a set of cores capable of parallel execution of threads. Each of the cores may run code that is provided with a progress meter that calculates the amount of work remaining to be performed on threads as they run on their respective cores. The data may be collected continuously, and may be used to alter the frequency, speed or other operating characteristic of the cores as well as groups of cores. The progress meters may be annotated into existing code.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: Jonathan M. Eastep, Ilya Sharapov, Rob F. Van Der Wijngaart, Richard J. Greco, Steve S. Sylvester, David N. Lombard
  • Publication number: 20160187944
    Abstract: Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: Jonathan M. Eastep, Ilya Sharapov, Richard J. Greco, Steve S. Sylvester, David N. Lombard
  • Publication number: 20160179173
    Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Applicant: Intel Corporation
    Inventors: JONATHAN M. EASTEP, ROHIT BANERJEE, RICHARD J. GRECO, ILYA SHARAPOV, DAVID N. LOMBARD, HARI K. NAGPAL
  • Patent number: 8688430
    Abstract: Embodiments of the present invention provide a system that simulates a load on a computer system. The system starts by collecting a set of sampled values from one or more monitors in the computer system during the execution of program code. Next, the system uses the set of sampled values to determine if one or more repeating computational phases occurs during the execution of the program code. If one or more repeating computational phases occurs, the system subsequently simulates a load on the computer system by executing portions of the program code that caused each repeating computational phase one or more times.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: April 1, 2014
    Assignee: Oracle America, Inc.
    Inventors: Lodewijk Bonebakker, Ilya Sharapov
  • Patent number: 8346087
    Abstract: Embodiments of a system that includes an array of chip modules (CMs) is described. In this system, a given CM in the array includes a semiconductor die that is configured to communicate data signals with one or more adjacent CMs through electromagnetic proximity communication using proximity connectors. Note that the proximity connectors are proximate to a surface of the semiconductor die. Moreover, the given CM is configured to communicate optical signals with other CMs through an optical signal path using optical communication, and the optical signals are encoded using wavelength-division multiplexing (WDM).
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: January 1, 2013
    Assignee: Oracle America, Inc.
    Inventors: Brian W. O'Krafka, Ashok V. Krishnamoorthy, John E. Cunningham, Xuehze Zheng, Ilya A. Sharapov, Ronald Ho
  • Publication number: 20120230695
    Abstract: Embodiments of a system that includes an array of chip modules (CMs) is described. In this system, a given CM in the array includes a semiconductor die that is configured to communicate data signals with one or more adjacent CMs through electromagnetic proximity communication using proximity connectors. Note that the proximity connectors are proximate to a surface of the semiconductor die. Moreover, the given CM is configured to communicate optical signals with other CMs through an optical signal path using optical communication, and the optical signals are encoded using wavelength-division multiplexing (WDM).
    Type: Application
    Filed: September 28, 2007
    Publication date: September 13, 2012
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Brian W. O'Krafka, Ashok V. Krishnamoorthy, John E. Cunningham, Xuehze Zheng, Ilya A. Sharapov, Ronald Ho
  • Patent number: 7865084
    Abstract: Embodiments of a system that includes an array of single-chip modules (CMs) are described. This array includes a first CM, a second CM coupled to the first CM, and a third CM coupled to the second CM. A given CM, which can be the first CM, the second CM or the third CM, includes a semiconductor die that is configured to communicate data signals with other CMs through electromagnetically coupled proximity communication. These proximity connectors are proximate to a surface of the semiconductor die. Moreover, the first CM and the third CM are configured to optically communicate optical signals with each other via the second CM through an optical signal path.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: January 4, 2011
    Assignee: Oracle America, Inc.
    Inventors: Ashok V. Krishnamoorthy, Ronald Ho, Brian W. O'Krafka, Ilya A. Sharapov, John E. Cunningham
  • Patent number: 7730470
    Abstract: A system for binary code instrumentation to reduce effective memory latency comprises a processor and memory coupled to the processor. The memory comprises program instructions executable by the processor to implement a code analyzer configured to analyze an instruction stream of compiled code executable at an execution engine to identify, for a given memory reference instruction in the stream that references data at a memory address calculated during an execution of the instruction stream, an earliest point in time during the execution at which sufficient data is available at the execution engine to calculate the memory address. The code analyzer generates an indication of whether the given memory reference instruction is suitable for a prefetch operation based on a difference in time between the earliest point in time and a time at which the given memory reference instruction is executed during the execution.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: June 1, 2010
    Assignee: Oracle America, Inc.
    Inventors: Ilya A. Sharapov, Andrew J. Over
  • Patent number: 7533141
    Abstract: System and method for the unique naming of resources in networked environments including peer-to-peer network environments. Embodiments may be used to generate network resource identifiers that uniquely identify resources such as processes over time and across the networked environment. One embodiment may be implemented as a resource name generator that generates unique identifiers for resources in networked environments. One embodiment may generate unique network resource identifiers for processes from information including, but not limited to, a host address that uniquely identifies on the network the host machine of the resource for which the unique network resource identifier is being generated, a current time (e.g. obtained from the host machine or alternatively from an external source such as an atomic time server), and a process identifier of the process that uniquely identifies the process among current processes on the host machine.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: May 12, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Neelakanth M. Nadgir, Jerome M. Verbeke, Ilya A. Sharapov, Gregory R. Ruetsch, Vu Trang, Michael J. Vernik
  • Publication number: 20090067851
    Abstract: Embodiments of a system that includes an array of single-chip modules (CMs) are described. This array includes a first CM, a second CM coupled to the first CM, and a third CM coupled to the second CM. A given CM, which can be the first CM, the second CM or the third CM, includes a semiconductor die that is configured to communicate data signals with other CMs through electromagnetically coupled proximity communication. These proximity connectors are proximate to a surface of the semiconductor die. Moreover, the first CM and the third CM are configured to optically communicate optical signals with each other via the second CM through an optical signal path.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 12, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Ashok V. Krishnamoorthy, Ronald Ho, Brian W. O'Krafka, Ilya A. Sharapov, John E. Cunningham
  • Patent number: 7395536
    Abstract: System and method for submitting and performing computational tasks in a distributed heterogeneous networked environment. Embodiments may allow tasks to be submitted and run in parallel on a network of heterogeneous computers implementing a variety of operating environments. In one embodiment, a user on an originating node may advertise code on the network. Peer nodes that respond to the advertisement may receive the code. A job to be executed by the code may be split into separate tasks to distributed to the peer nodes that received the code. These tasks may be advertised on the network. Tasks may be assigned to peer nodes that respond to the task advertisements. The peer nodes may then work on the assigned tasks. Once a peer node's work on a task is completed, the peer node may return the results of the task to the originating node.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: July 1, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Jerome M. Verbeke, Neelakanth M. Nadgir, Gregory R. Ruetsch, Ilya A. Sharapov, Michael J. Vernik, Vu Trang
  • Patent number: 7333444
    Abstract: One embodiment of the present invention provides a system for generating an interconnection network. During operation, the system associates an n-bit binary identifier with each node in the interconnection network. The system also groups the n bits of each binary identifier into h overlapping sets a1, a2, . . . ah, wherein the sets a1, a2, . . . ah cover all of the n bits. For each set ai, the system forms fully connected clusters of nodes by creating a direct point-to-point link between any two nodes that have binary identifiers that differ in bits of the set a1 but are the same in other bit positions. Note that by varying the amount of overlap and the pattern of overlap between the overlapping sets, a1, a2, . . . ah, the interconnection network can be configured to accommodate different redundancy requirements.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: February 19, 2008
    Assignee: Sun Microsystems, Inc.
    Inventor: Ilya A. Sharapov