Abstract: A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.

Abstract: An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t?1)/(codeword_len?3)?X<(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.

Abstract: A process and apparatus are provided for tiling objects, such as design memories, in one or more respective object locations in a layout pattern. For each object, the following steps are performed recursively based on a comparison of at least one of a capacity and a width of the object and that of the respective object location: (1) do nothing; (2) reconfigure the object to have a different capacity and/or width; and (3) split the object into two or more separate objects. The recursion is repeated for each reconfigured object and each separated object.

Abstract: An RRAM design having linear BIST memory and rectangular BIST memory, the improvement comprising at least one of the linear BIST memory and the rectangular BIST memory formed only of flipflops and logic cells.

Abstract: A memory generation and placement flow system that receives a customer memory design and places the customer memory design within a customizable standardized integrated circuit design. The memory generation and placement flow system includes a memory librarian tool, a memory estimator tool, and a memory placer tool.