Abstract: A high speed communication apparatus with means for reducing timing uncertainty providing a high accuracy of transferring and receiving signals by intelligent skew calibration of the apparatus. The system for reducing timing uncertainty of a communication apparatus comprises a plurality of driving registers for transmitting signals; a plurality of receiving registers for receiving signals; a main clock for generating a main clock signal; a reference clock for generating reference signals for calibrating the registers; and a plurality of phase shift means comprising at least one set of phase shift means associated with each said plurality of registers, for the relative alignment of the register's timing within each plurality.

Abstract: A high speed communication apparatus with means for reducing timing uncertainty providing a high accuracy of transferring and receiving signals by intelligent skew calibration of the apparatus. The system for reducing timing uncertainty of a communication apparatus comprises a plurality of driving registers for transmitting signals; a plurality of receiving registers for receiving signals; a main clock for generating a main clock signal; a reference clock for generating reference signals for calibrating the registers; and a plurality of phase shift means comprising at least one set of phase shift means associated with each said plurality of registers, for the relative alignment of the register's timing within each plurality.

Abstract: A data transmission means and method employing the phase noise characteristics within the receiving registers to measure and control the characteristics of the channel as a function of the data pattern and to compensate for production tolerances within the channel by altering the timing characteristics of the signal at either the transmitter or receiver as a function of the data. Time offsets between different signals that form the communication channel are measured for different frequencies and/or for different data patterns transmitted through the channel and stored to compensate for an inter-signal skew by performing relative alignment of the measured offsets to a main clock edge.

Abstract: The present invention relates generally to data processing systems, in particular, to high speed data communication and chip-to-chip data transfer.

Abstract: Automatic test equipment for memory device testing with elements providing a high accuracy of transferring and receiving signals when testing a semiconductor device under test (DUT) by intelligent skew calibration of a timing system. The device for automatic skew calibration of a transceiver comprises a plurality of input registers for transmitting signals; a plurality of output registers for receiving signals; a main clock driver for generating a main clock signal; a reference clock driver for generating reference signals for calibrating the registers; the reference clock driver being associated with the main clock driver; and a plurality of phase shifters comprising at least one set of phase shifters associated with each plurality of registers, for the relative alignment of the register's timing within each plurality. The calibration is performed using a common time base which is distributed by means of a transmission line having predetermined wave characteristics.