Patents by Inventor Ilya Wagner
Ilya Wagner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220113353Abstract: In an embodiment, an input-output (IO) device may include an IO controller and a debug controller. The IO controller may process IO data packets. The debug controller may be to: receive a first debug packet from a host system via an in-band connection, process the first debug packet to extract a command generated by the host system, and execute the extracted command to debug the IO device. Other embodiments are described and claimed.Type: ApplicationFiled: December 23, 2021Publication date: April 14, 2022Inventors: Aruni P. Nelson, Abdul R. Ismail, Ashok Mishra, Enrico David Carrieri, Ilya Wagner
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Patent number: 9753832Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.Type: GrantFiled: June 28, 2013Date of Patent: September 5, 2017Assignee: Intel CorporationInventors: Ilya Wagner, Matthew C. Merten, Frank Binns, Christine E. Wang, Mayank Bomb, Tong Li, Thilo Schmitt, M D A. Rahman
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Patent number: 9645882Abstract: A state matcher for a logic circuit may detect at least one of a buggy state of the logic circuit, a precursor to a buggy state of the logic circuit and a verified state of the logic circuit based on a plurality of signal values indicative of a state of the logic circuit. A recovery controller for a microprocessor may reconfigure the microprocessor to a trusted feature mode in response to receiving a signal indicating that the microprocessor is in a predefined state and operate the microprocessor in the trusted feature mode for a predetermined period of time.Type: GrantFiled: July 23, 2008Date of Patent: May 9, 2017Assignee: The Regents of the University of MichiganInventors: Valeria Bertacco, Todd Michael Austin, Ilya Wagner
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Publication number: 20150006868Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Ilya Wagner, Matthew C. Merten, Frank Binns, Christine E. Wang, Mayank Bomb, Tong Li, Thilo Schmitt, MD A. Rahman
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Patent number: 8806285Abstract: Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.Type: GrantFiled: May 31, 2012Date of Patent: August 12, 2014Assignee: Intel CorporationInventors: Alaa R. Alameldeen, Ilya Wagner, Zeshan A. Chishti, Wei Wu, Christopher B. Wilkerson
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Publication number: 20130326263Abstract: Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Inventors: Alaa R. Alameldeen, Ilya Wagner, Zeshan A. Chishti, Wei Wu, Christopher B. Wilkerson
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Patent number: 8365110Abstract: A computer executable tool facilitates integrated circuit design and debugging by working directly at the Register Transfer Level, where most design activities take place. The tool determines when an integrated circuit design produces incorrect output responses for a given set of input vectors. The tool accesses the expected responses and returns the signal paths in the integrated circuit that are responsible for the errors along with suggested changes for fixing the errors. The tool may operate at the RTL, which is above the gate-level abstraction which means that the design errors will be much more readily understood to the designer, and may improve scalability and efficiency.Type: GrantFiled: May 27, 2008Date of Patent: January 29, 2013Assignee: The Regents of the University of MichiganInventors: Kai-Hui Chang, Ilya Wagner, Igor Markov, Valeria Bertacco
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Publication number: 20110087861Abstract: A post-silicon validation technique is able to craft randomized executable code, with known final outcomes, as a verification test that is executable on a hardware, such as a prototype microprocessor. A verification device is able to generate the test, in the form of programs, in such a way that at the end of the execution, the initial state of the test hardware is restored. Therefore, the final state of such a reversible program is known a priori. The technique may use a program generation algorithm, agnostic to any particular instruction set on the test hardware. In some examples, that algorithm is executed on the test hardware to generate the verification test, which is then executed on that test hardware. In other examples, the verification test is generated on another processor coupled to the test hardware. In either case, the verification test may contain initial and inverse operations determined from the test hardware.Type: ApplicationFiled: October 12, 2010Publication date: April 14, 2011Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Valeria Bertacco, Ilya Wagner
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Publication number: 20090089615Abstract: A state matcher for a logic circuit may detect at least one of a buggy state of the logic circuit, a precursor to a buggy state of the logic circuit and a verified state of the logic circuit based on a plurality of signal values indicative of a state of the logic circuit. A recovery controller for a microprocessor may reconfigure the microprocessor to a trusted feature mode in response to receiving a signal indicating that the microprocessor is in a predefined state and operate the microprocessor in the trusted feature mode for a predetermined period of time.Type: ApplicationFiled: July 23, 2008Publication date: April 2, 2009Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Valeria Bertacco, Todd Michael Austin, Ilya Wagner
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Publication number: 20080295043Abstract: A computer executable tool facilitates integrated circuit design and debugging by working directly at the Register Transfer Level, where most design activities take place. The tool determines when an integrated circuit design produces incorrect output responses for a given set of input vectors. The tool accesses the expected responses and returns the signal paths in the integrated circuit that are responsible for the errors along with suggested changes for fixing the errors. The tool may operate at the RTL, which is above the gate-level abstraction which means that the design errors will be much more readily understood to the designer, and may improve scalability and efficiency.Type: ApplicationFiled: May 27, 2008Publication date: November 27, 2008Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Kai-Hui Chang, Ilya Wagner, Igor Markov, Valeria Bertacco