Patents by Inventor Ilya Yusim

Ilya Yusim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for efficient device testing and validation of fast transients
    Patent number: 10068044
    Abstract: The time to test integrated circuits is increasing as a function of the complexity of integrated circuits and processes used to fabricate the integrated circuits. Embodiments of this disclosure include systems and methods for reducing the time to integrated circuits by reducing the number of devices individually modeled. Embodiments can reduce the number of modeled devices by combining two or more devices into a single combined device that models all discrete devices, but in a reduced form.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 4, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yinghong Zhou, Ilya Yusim, Joel Phillips
  • System and method for fault sensitivity analysis of mixed-signal integrated circuit designs
    Patent number: 9026963
    Abstract: An apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: May 5, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Ilya Yusim, Zhipeng Liu
  • System and method for fault sensitivity analysis of mixed-signal integrated circuit designs
    Patent number: 8683400
    Abstract: A apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: March 25, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Ilya Yusim, Zhipeng Liu