Patents by Inventor Ilyas Mohammed

Ilyas Mohammed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12293993
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: October 13, 2023
    Date of Patent: May 6, 2025
    Assignee: Adeia Semiconductor Inc.
    Inventors: Javier A. DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Publication number: 20250142942
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Application
    Filed: October 3, 2024
    Publication date: May 1, 2025
    Inventors: Javier A. DeLaCruz, Steven L. Teig, Ilyas Mohammed, Eric M. Nequist
  • Publication number: 20250140766
    Abstract: A chip package assembly is disclosed that includes an integrated circuit chip and an optical interconnect system. The optical interconnect system has a first optical transmitter having a plurality of first microLEDs and a first optical receiver having a plurality of light sensors. The first optical transmitter and first optical receiver communicate with a respective second external optical receiver and second external optical transmitter of one or more external chip package assemblies. The external optical transmitter transmits an unmodulated optical light signal to the light sensor indicating whether first microLEDs of the external optical transmitter are in the first “on” state or the first “off” state. The light sensors convert the received and second corresponding unmodulated optical light signal to an electrical signal.
    Type: Application
    Filed: October 28, 2024
    Publication date: May 1, 2025
    Inventor: Ilyas Mohammed
  • Publication number: 20250125248
    Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.
    Type: Application
    Filed: July 24, 2024
    Publication date: April 17, 2025
    Inventors: Belgacem Haba, Ilyas Mohammed, Rajesh Katkar, Gabriel Z. Guevara, Javier A. DeLaCruz, Shaowu Huang, Laura Wills Mirkarimi
  • Patent number: 12278215
    Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: April 15, 2025
    Assignee: Adeia Semiconductor Inc.
    Inventors: Javier A. DeLaCruz, Don Draper, Belgacem Haba, Ilyas Mohammed
  • Patent number: 12270970
    Abstract: Direct-bonded lamination for improved image clarity in optical devices is provided. An example process planarizes and plasma-activates optical surfaces to be laminated together, then forms direct bonds between the two surfaces without an adhesive or adhesive layer. This process provides improved optics with higher image brightness, less light scattering, better resolution, and higher image fidelity. The direct bonds also provide a refractory interface tolerant of much higher temperatures than conventional optical adhesives. The example process can be used to produce many types of improved optical components, such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and mirrored waveguides for smartglasses and head-up displays (HUDs), which provide better image quality and elimination of the dark visual lines that are apparent to a human viewer when conventional adhesives are used in conventional lamination.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: April 8, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Belgacem Haba, Rajesh Katkar, Ilyas Mohammed
  • Publication number: 20250102746
    Abstract: The technology generally relates to high bandwidth memory (HBM) packages and processor packages that have optical connectivity. Disclosed systems and methods herein allow for HBM dies that are interconnected with an optical interface in a manner that allows for compact, high-performance computing. An HBM package can be cooled using a cooling unit that is distinct from the processor package. In addition, the cooling unit can be configured so as to provide thermal contact with a subset of high-power components within the HBM package.
    Type: Application
    Filed: September 26, 2023
    Publication date: March 27, 2025
    Inventors: Horia Alexandru Toma, Zuowei Shen, Ilyas Mohammed, Yingying Wang, William F. Edwards, Jr.
  • Publication number: 20250096168
    Abstract: A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 ?m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 ?m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives.
    Type: Application
    Filed: December 3, 2024
    Publication date: March 20, 2025
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Publication number: 20250087566
    Abstract: A package substrate for a microelectronic package assembly includes an inorganic core body, such as a ceramic core body, with embedded capacitors and at least one conductive through via extending through the core body. The structure of the inorganic core body allows for at least one redistribution layer to be built-up directly onto the inorganic core body, without the use of an intermediate carrier or interposer.
    Type: Application
    Filed: August 15, 2024
    Publication date: March 13, 2025
    Inventor: Ilyas Mohammed
  • Publication number: 20250046516
    Abstract: A microelectronic package assembly is disclosed that implements a capacitor carrier capable of providing package warpage control and that eliminates the need to only bond chip capacitors directly to a surface of the package substrate. The capacitor carrier may be composed of a material that has a high coefficient of thermal expansion and a high Young's modulus. A capacitor carrier with these characteristics can eliminate the need for a traditional stiffener in the chip package.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 6, 2025
    Inventors: Scott Lee Kirkman, Nam Hoon Kim, Ilyas Mohammed
  • Patent number: 12218059
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: February 4, 2025
    Assignee: Adeia Semiconductor Inc.
    Inventors: Ilyas Mohammed, Steven L. Teig, Javier A. DeLaCruz
  • Publication number: 20250028661
    Abstract: The disclosure provides for high bandwidth processing through the sharing of memory dies over a plurality of computing dies via an optical interchange. The optical interchange may be configured so as to operate as both an optical switch and optical demultiplexer. The optical switch configuration for the optical interchange allows for data to be written from any computing die to one of a plurality of memory dies via an optical connection. The optical demultiplexer configuration allows for data to be broadcast from a memory die to a plurality of the computing dies.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Inventors: Horia Alexandru Toma, Zuowei Shen, William F. Edwards, JR., Gurushankar Rajamani, Hong Liu, Ilyas Mohammed
  • Patent number: 12191267
    Abstract: A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 ?m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 ?m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: January 7, 2025
    Assignee: Adeia Semiconductor Technologies, LLC
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 12142528
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: November 12, 2024
    Assignee: Adeia Semiconductor Inc.
    Inventors: Javier A. DeLaCruz, Steven L. Teig, Ilyas Mohammed, Eric M. Nequist
  • Patent number: 12136605
    Abstract: Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: November 5, 2024
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Rajesh Katkar, Ilyas Mohammed, Cyprian Emeka Uzoh
  • Patent number: 12124035
    Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: October 22, 2024
    Assignee: Adeia Semiconductor Technologies LLC
    Inventors: Belgacem Haba, Ilyas Mohammed, Gabriel Z. Guevara, Min Tao
  • Publication number: 20240347443
    Abstract: Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.
    Type: Application
    Filed: October 19, 2023
    Publication date: October 17, 2024
    Inventors: Belgacem Haba, Stephen Morein, Ilyas Mohammed, Rajesh Katkar, Javier A. Delacruz
  • Publication number: 20240345399
    Abstract: An optical apparatus is provided comprising: first and second optical waveguides disposed in a substrate such that light reflected by a beam splitting optical element of the first waveguide passes between beam splitting elements of the second waveguide.
    Type: Application
    Filed: January 9, 2024
    Publication date: October 17, 2024
    Inventors: Ilyas Mohammed, Rajesh Katkar, Belgacem Haba
  • Publication number: 20240312957
    Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.
    Type: Application
    Filed: December 28, 2023
    Publication date: September 19, 2024
    Inventors: Javier A. DeLaCruz, Don Draper, Belgacem Haba, Ilyas Mohammed
  • Patent number: RE50272
    Abstract: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: January 14, 2025
    Assignee: Adeia Semiconductor Technologies LLC
    Inventors: Belgacem Haba, Ilyas Mohammed, Rajesh Katkar