Abstract: A substrate processing apparatus includes a chamber configure to provide a space for processing a substrate, a substrate support configured to support the substrate in the chamber, an upper supply port provided in an upper portion of the chamber and configured to supply a supercritical fluid on an upper surface of the substrate, a recess provided in an upper wall of the chamber and having a diffuser shape whose diameter gradually increases from an outlet of the upper supply port, and a fluidic baffle disposed in the recess between the upper supply port and the substrate and including unit cells repeatedly arranged in a space with same phases and geometric sizes and in fluid communication with each other.

Abstract: An electronic device for reducing noise occurring in measuring a distance to an external object is provided.

Abstract: An electronic device may include a housing including a first surface, a second surface, and a side surface, a camera module disposed at a position aligned with an opening formed in the first surface, a decorative member including a first portion connected to the first surface at a position at which the opening is formed and having a hollow, a second portion extending from the first portion and surrounding the hollow, and a window seated on the second portion, a processor, and a memory, wherein the camera module includes at least one lens, and a lens barrel including a cylindrical lower portion, an extension portion extending from the lower portion, and a cylindrical upper portion extending from the extension portion, and the distance from the lower portion to the first portion is smaller than the distance from the upper portion to the window.

Abstract: An electronic device includes a communication circuit, a light source for emitting light of set frequencies, an image sensor for acquiring reflected light of the emitted light, a memory for storing offset values for respective reference frequencies of the set frequencies, and a processor. The processor is configured to receive a distance measurement input, identify whether the communication circuit is activated, determine that, in response to identification that the communication circuit is activated, a first frequency distinguished from a frequency used by the activated communication circuit is a frequency of the emitted light among the configured frequencies, acquire information on a distance between the electronic device and an external object, based on the reflected light of the emitted light of the first frequency, and acquire corrected distance information by applying an offset of the first frequency to the acquired distance information.

Abstract: Various embodiments of the present invention relate to a method for controlling an actuator. The present invention can detect a haptic generation event through a sensor unit, check data of an actuator and data of a human receptor stored in a memory in response to the haptic generation event, calculate a driving voltage of the actuator on the basis of the checked data of the actuator and the checked data of the human receptor, and drive the actuator with the calculated driving voltage. Other embodiments are also possible.

Abstract: An electronic device may include a housing including a first surface, a second surface, and a side surface, a camera module disposed at a position aligned with an opening formed in the first surface, a decorative member including a first portion connected to the first surface at a position at which the opening is formed and having a hollow, a second portion extending from the first portion and surrounding the hollow, and a window seated on the second portion, a processor, and a memory, wherein the camera module includes at least one lens, and a lens barrel including a cylindrical lower portion, an extension portion extending from the lower portion, and a cylindrical upper portion extending from the extension portion, and the distance from the lower portion to the first portion is smaller than the distance from the upper portion to the window.

Abstract: An electronic device for reducing noise occurring in measuring a distance to an external object is provided.

Abstract: Various embodiments of the present invention relate to a method for controlling an actuator. The present invention can detect a haptic generation event through a sensor unit, check data of an actuator and data of a human receptor stored in a memory in response to the haptic generation event, calculate a driving voltage of the actuator on the basis of the checked data of the actuator and the checked data of the human receptor, and drive the actuator with the calculated driving voltage. Other embodiments are also possible.

Abstract: A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.

Abstract: A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.

Abstract: A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.

Abstract: A memory self-testing system, apparatus, and method are provided which allow for testing for a plurality of bit errors and passing memory arrays having an error level which is correctable using selected error correction coding. An exemplary system embodiment includes a memory array, a comparator, an integrator, and a test control circuit. The memory array is adapted to store input test data and output stored test data during a plurality of memory read and write test operations. The comparator compares the input test data and the stored test data for a plurality of bit positions, and provides a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions. The integrator receives the corresponding error signal and maintains the corresponding error signal for each bit position during the plurality of test operations.

Abstract: A built-in, self-test (BIST) network employs a hierarchy of Universal BIST schedulers (UBSs) for scheduling and coordinating testing of elements, such as regular structure BISTed (RSB) elements and random logic BISTed (RLB) elements. Individual UBSs are preferably positioned in local areas, or sections, of an integrated circuit for testing of RSB and RLB elements within the local area. Testing of RSB and RLB elements within the local area allows the BIST network to minimize effects of delay and clock skew by employing relatively short interconnect routing between BISTed elements. Each of the individual UBSs are, in turn, controlled by a master UBS (MUBS) via simplified timing of control signals. The MUBS also may interface with an external testing device that initiates BISTed testing.

Abstract: A reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device generates a spare address in real time corresponding to a faulty address. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. The output signal includes a spare control signal that directs components to look to the output of the spare memory.

Abstract: A reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device generates a spare address in real time corresponding to a faulty address. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. The output signal includes a spare control signal that directs components to look to the output of the spare memory.

Abstract: A method is provided for determining the location of faulty components in a computer memory array on a chip and for providing a software repair procedure. According to the method, the location of faulty components in a computer memory array is determined by successively reading and writing to locations in the array according to an algorithm. If a faulty component is detected, it is determined whether a spare component in a spare memory array on the chip is available. If a spare component is available, a spare component is designated to correspond to the faulty component. A look up table on the same chip stores information representing the location of the faulty component associated with information representing the location of the corresponding spare component.

Abstract: This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in multiple stages in order to optimize the efficiency of continuous processing and to apply a single waiting period to multiple SBRIC_RSs where, for example, BIST includes retention testing; dividing resource controllers or SBRIC_RSs corresponding to one or more RSB elements into a matrix such that each SBRIC_RS executes the BIST of its memory elements concurrently and/or successively depending on the SBRIC_RS's position in the matrix; and passing a token to initiate processing of a set of SBRIC_RSs in the matrix through a level signal rather than a pulse signal in order to ensure that the signal is not lost.

Abstract: A memory device has first and second sets of memory cells. Each of the cells in the second set is a neighboring cell corresponding to a respective cell of the first set. A data generating function generates a first pattern and a second pattern. A controller causes the first pattern to be written in the first set of memory cells, causes each cell in the second set of memory cells to be read simultaneously while the corresponding neighboring cell in the first set of memory cells is being written to, and causes a datum to be read from each cell in the second set of memory cells after the corresponding neighboring cell in the first set of memory cells is written to. An output data evaluator determines whether the data read from the second set of memory cells match the second pattern, and detects a fault in the memory device, if the data read do not match the second pattern.

Abstract: A method and apparatus are described for detecting an optimized set of predetermined faults in a memory device which ensure an acceptable quality level. The method and apparatus comprise a BIST March algorithm optimized to accelerate the testing time by reducing the number of read/write operations necessary to detect a set of predetermined faults.

Abstract: Memory test hardware is provided for generating signals for testing a first memory array and a second memory array. The first memory array and the second memory array may be any two of main memory array, a spare memory array, and reconfiguration memory array, or the apparatus may be adapted for testing all three memory arrays. The memory test hardware may include a controller for generating control signals, a data generator coupled to the controller for generating data signals, and an address generator coupled to the controller for generating address signals. The test device may further include an output data evaluator and repair unit for receiving signals from the main memory array and the spare memory array and for detecting faults in those arrays.