Patents by Inventor Ilyoung Kim

Ilyoung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200319306
    Abstract: An electronic device for reducing noise occurring in measuring a distance to an external object is provided.
    Type: Application
    Filed: March 30, 2020
    Publication date: October 8, 2020
    Inventors: Ilyoung KIM, Hyunju YANG, Kihuk LEE
  • Patent number: 10751838
    Abstract: A laser cutting apparatus and a laser cutting method are provided. A laser cutting method includes: preparing an object on a stage; cutting the object into a set shape by relatively moving and irradiating a laser beam along the set shape with respect to the object; and performing uniform heating compensation to reduce accumulation of thermal energy of the laser beam resulting from a change of speed at a shift point where a travelling direction of the laser beam with respect to the object changes.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 25, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ilyoung Jeong, Gyoowan Han, Jaeil Kim, Kuhyun Kang, Soobum Park
  • Patent number: 10502212
    Abstract: A motor-operated compressor includes a casing having an inner space in which a driving motor, an orbiting scroll and a fixed scroll are accommodated, and a controller provided outside the casing. The casing includes an intake hole formed at a side adjacent to the controller and an exhaust hole formed at a side adjacent to the fixed scroll on the basis of the driving motor. The casing includes a communication passage formed between the casing and a stator of the driving motor, such that a refrigerant introduced into the inner space through the intake hole is introduced into the suction chamber through the driving motor. A back pressure space supporting the orbiting scroll is sealed by oil. The stator has teeth on its inner circumferential surface and protrusions on its outer circumferential surface, each protrusion being located within a width range of each tooth.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 10, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Junggu Lee, Taekyoung Kim, Yicheol Choi, Joohyung Kim, Ilyoung Park, Bumsuk Kim, Junyoung Lim
  • Publication number: 20190354186
    Abstract: Various embodiments of the present invention relate to a method for controlling an actuator. The present invention can detect a haptic generation event through a sensor unit, check data of an actuator and data of a human receptor stored in a memory in response to the haptic generation event, calculate a driving voltage of the actuator on the basis of the checked data of the actuator and the checked data of the human receptor, and drive the actuator with the calculated driving voltage. Other embodiments are also possible.
    Type: Application
    Filed: January 5, 2018
    Publication date: November 21, 2019
    Inventors: Yudong BAE, Jeongseok LEE, Jaeyoung HUH, Donggyu KIM, Ilyoung KIM, Kwonho SONG, Yanghee LEE
  • Publication number: 20190264689
    Abstract: An electric compressor includes a first scroll and a second scroll engaged with the first scroll and making an orbiting motion to form a pair of two compression chambers with the first scroll. A rotary shaft is eccentrically coupled to the second scroll and is rotatably supported by a bearing member. A frame is fixed to an opposite side of the first scroll from the second scroll with the second scroll being interposed between the frame and the first scroll. The frame includes a bearing support portion, and the bearing member is inserted into and fixed to the bearing support member with an interference fit.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 29, 2019
    Applicant: LG ELECTRONICS INC.
    Inventors: Ilyoung PARK, Joohyung KIM, Taekyoung KIM
  • Publication number: 20190229325
    Abstract: A negative active material for a rechargeable lithium battery and a rechargeable lithium battery including the same are disclosed, and the negative active material includes a primary particle of a crystalline carbon-based material and secondary particle that is an assembly of the primary particles, wherein a ratio of an average particle diameter (D50) of the secondary particle relative to an average particle diameter (D50) of the primary particle (average particle diameter (D50) of the secondary particle/average particle diameter (D50) of the primary particle) ranges from about 1.5 to about 5 and an aspect ratio of the primary particle ranges from about 1 to about 7.
    Type: Application
    Filed: July 10, 2017
    Publication date: July 25, 2019
    Inventors: Ji Woo AHN, Dongwoo KIM, Jaehou NAH, Bumjin CHANG, Yurim CHA, Yeonjoo CHOI, Ilyoung CHOI
  • Patent number: 10332842
    Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kiseok Lee, Sooho Shin, Juik Lee, Jun Ho Lee, Kwangmin Kim, Ilyoung Moon, Jemin Park, Bumseok Seo, Chan-Sic Yoon, Hoin Lee
  • Patent number: 8201032
    Abstract: A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: June 12, 2012
    Assignee: Agere Systems Inc.
    Inventors: Donald A. Evans, Ilyoung Kim
  • Publication number: 20080016418
    Abstract: A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 17, 2008
    Applicant: AGERE SYSTEMS INC.
    Inventors: Donald Evans, Ilyoung Kim
  • Publication number: 20060090106
    Abstract: A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.
    Type: Application
    Filed: October 27, 2004
    Publication date: April 27, 2006
    Inventors: Donald Evans, Ilyoung Kim
  • Publication number: 20060048031
    Abstract: A memory self-testing system, apparatus, and method are provided which allow for testing for a plurality of bit errors and passing memory arrays having an error level which is correctable using selected error correction coding. An exemplary system embodiment includes a memory array, a comparator, an integrator, and a test control circuit. The memory array is adapted to store input test data and output stored test data during a plurality of memory read and write test operations. The comparator compares the input test data and the stored test data for a plurality of bit positions, and provides a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions. The integrator receives the corresponding error signal and maintains the corresponding error signal for each bit position during the plurality of test operations.
    Type: Application
    Filed: September 1, 2004
    Publication date: March 2, 2006
    Applicant: Agere Systems, Inc.
    Inventors: Duane Aadsen, Ilyoung Kim, Ross Kohler, Richard McPartland
  • Publication number: 20040128600
    Abstract: A built-in, self-test (BIST) network employs a hierarchy of Universal BIST schedulers (UBSs) for scheduling and coordinating testing of elements, such as regular structure BISTed (RSB) elements and random logic BISTed (RLB) elements. Individual UBSs are preferably positioned in local areas, or sections, of an integrated circuit for testing of RSB and RLB elements within the local area. Testing of RSB and RLB elements within the local area allows the BIST network to minimize effects of delay and clock skew by employing relatively short interconnect routing between BISTed elements. Each of the individual UBSs are, in turn, controlled by a master UBS (MUBS) via simplified timing of control signals. The MUBS also may interface with an external testing device that initiates BISTed testing.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Inventors: Ilyoung Kim, Laurence Reeves, Paul W. Rutkowski, Jing Wu
  • Patent number: 6397349
    Abstract: A reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device generates a spare address in real time corresponding to a faulty address. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. The output signal includes a spare control signal that directs components to look to the output of the spare memory.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: May 28, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Frank P. Higgins, Ilyoung Kim, Goh Komoriya, Hai Quang Pham, Yervant Zorian
  • Publication number: 20020019957
    Abstract: A reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device generates a spare address in real time corresponding to a faulty address. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. The output signal includes a spare control signal that directs components to look to the output of the spare memory.
    Type: Application
    Filed: October 13, 1998
    Publication date: February 14, 2002
    Applicant: AGERE SYSTEMS GUARDIAN CORP.
    Inventors: FRANK P. HIGGINS, ILYOUNG KIM, GOH KOMORIYA, HAI QUANG PHAM, YERVANT ZORIAN
  • Patent number: 6317846
    Abstract: A method is provided for determining the location of faulty components in a computer memory array on a chip and for providing a software repair procedure. According to the method, the location of faulty components in a computer memory array is determined by successively reading and writing to locations in the array according to an algorithm. If a faulty component is detected, it is determined whether a spare component in a spare memory array on the chip is available. If a spare component is available, a spare component is designated to correspond to the faulty component. A look up table on the same chip stores information representing the location of the faulty component associated with information representing the location of the corresponding spare component.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: November 13, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Frank P. Higgins, Ilyoung Kim, Yervant Zorian
  • Patent number: 6237123
    Abstract: This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in multiple stages in order to optimize the efficiency of continuous processing and to apply a single waiting period to multiple SBRIC_RSs where, for example, BIST includes retention testing; dividing resource controllers or SBRIC_RSs corresponding to one or more RSB elements into a matrix such that each SBRIC_RS executes the BIST of its memory elements concurrently and/or successively depending on the SBRIC_RS's position in the matrix; and passing a token to initiate processing of a set of SBRIC_RSs in the matrix through a level signal rather than a pulse signal in order to ensure that the signal is not lost.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: May 22, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Ilyoung Kim, Paul William Rutkowski, Yervant Zorian
  • Patent number: 6216241
    Abstract: A memory device has first and second sets of memory cells. Each of the cells in the second set is a neighboring cell corresponding to a respective cell of the first set. A data generating function generates a first pattern and a second pattern. A controller causes the first pattern to be written in the first set of memory cells, causes each cell in the second set of memory cells to be read simultaneously while the corresponding neighboring cell in the first set of memory cells is being written to, and causes a datum to be read from each cell in the second set of memory cells after the corresponding neighboring cell in the first set of memory cells is written to. An output data evaluator determines whether the data read from the second set of memory cells match the second pattern, and detects a fault in the memory device, if the data read do not match the second pattern.
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: April 10, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Larry Ray Fenstermaker, Frank P. Higgins, Ilyoung Kim, James Louis Lewandowski, Jeffrey Jay Nagy
  • Patent number: 6205564
    Abstract: A method and apparatus are described for detecting an optimized set of predetermined faults in a memory device which ensure an acceptable quality level. The method and apparatus comprise a BIST March algorithm optimized to accelerate the testing time by reducing the number of read/write operations necessary to detect a set of predetermined faults.
    Type: Grant
    Filed: June 2, 1997
    Date of Patent: March 20, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Ilyoung Kim, Yervant Zorian
  • Patent number: 6175936
    Abstract: Memory test hardware is provided for generating signals for testing a first memory array and a second memory array. The first memory array and the second memory array may be any two of main memory array, a spare memory array, and reconfiguration memory array, or the apparatus may be adapted for testing all three memory arrays. The memory test hardware may include a controller for generating control signals, a data generator coupled to the controller for generating data signals, and an address generator coupled to the controller for generating address signals. The test device may further include an output data evaluator and repair unit for receiving signals from the main memory array and the spare memory array and for detecting faults in those arrays.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: January 16, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Frank P. Higgins, Ilyoung Kim
  • Patent number: 6108802
    Abstract: A variety of FIFOs, including single and dual port, RAM-type and/or having a ring-type addressing mechanism, are tested by causing the FIFOs to execute a test method comprised of a series of steps. Upon execution, the steps cause the FIFO to manifest a variety of faults. This test method manifests faults by monitoring the outcome of operations and the values of particular flags indicative of normal FIFO operation.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: August 22, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Ilyoung Kim, James Louis Lewandowski