Abstract: A semiconductor device includes a barrier rib separating the source/drain region into a plurality of parts. A first part of the plurality of parts of the source/drain region includes a first epitaxial layer having a lower end disposed on the active pattern and a sidewall part extending from the lower end in a third direction crossing first and second directions and connected to the channel pattern. A second epitaxial layer is disposed on the first epitaxial layer and has a composition different from a composition of the first epitaxial layer. In a cross-section cut from the center of the source/drain region in the first direction to the second and third directions, a lower end of the first epitaxial layer of the first part of the plurality of parts of the source/drain region has an asymmetric shape around an axis extending in the third direction.

Abstract: An integrated circuit device includes a substrate having a front side and a back side opposite to the front side and including a fin-type active region in the front side and a substrate recess in the back side, an isolation film in the substrate defining the fin-type active region, a source/drain region on the fin-type active region, a contact plug above the substrate, a backside power rail at least partially filling the substrate recess, and a via power rail electrically connected to the contact plug, the via power rail extending into the isolation film and connected to the backside power rail. A side surface of the backside power rail and a side surface of the via power rail form an obtuse angle at a portion where the backside power rail is connected to the via power rail.

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

Abstract: In a method for manufacturing a semiconductor device, comprising; forming mold insulation patterns on a substrate, forming an oxide semiconductor layer conformally on sidewalls and upper surfaces of the mold insulation patterns and the substrate, forming a first metal oxide layer on the oxide semiconductor layer, patterning the first sacrificial layer, the first metal oxide layer, and the oxide semiconductor layer to form a first structure including a preliminary first metal oxide layer pattern, a preliminary oxide semiconductor layer pattern and a first sacrificial layer pattern stacked, forming a preliminary second metal oxide layer pattern selectively on a sidewall of the preliminary oxide semiconductor layer pattern, removing selective portions of the first structure and the preliminary second metal oxide layer pattern to form an oxide semiconductor layer pattern, a first metal oxide layer pattern, and a second metal oxide layer pattern.

Abstract: An example semiconductor device includes a bit line structure and a bit line capping pattern that are stacked on a memory cell array region. The device further includes a peripheral gate structure including a peripheral gate dielectric layer, a peripheral gate electrode, and a peripheral gate capping pattern that are stacked on a peripheral circuit region. The device further includes a gate spacer on a side surface of the peripheral gate structure, a first peripheral interlayer insulating layer covering the peripheral gate structure and the gate spacer, and a first peripheral contact plug penetrating through the first peripheral interlayer insulating layer. The bit line capping pattern includes a lower bit line capping layer and an upper bit line capping layer that are stacked. A material of the upper bit line capping layer is same as a material of the first peripheral interlayer insulating layer.

Abstract: A semiconductor memory device according to an embodiment includes: a substrate; a bit line positioned on the substrate and extending in a first direction; a channel accommodating insulating layer positioned on the substrate, and defining a channel trench exposing the bit line and extending in a second direction crossing the first direction; a channel layer extending along a bottom surface and a side surface of the channel trench and contacting the bit line; a word line positioned in the channel trench and extending in the second direction; a gate insulating layer positioned between the channel layer and the word line; and a capacitor structure positioned on the channel layer and electrically connected to the channel layer, in which the channel layer has a double layer structure of an oxide semiconductor layer and a first graphene layer.

Abstract: A chemical mechanical polishing apparatus according to an example embodiment includes a polishing platen; a polishing pad which is located on the polishing platen and includes a polishing surface; a slurry supplier configured to supply a slurry to the polishing pad; a polishing head which is located above the polishing pad and configured to mount a wafer thereon; and an additional CMP process condition generator which generates an additional chemical mechanical polishing (CMP) process condition according to a type of residue when there is a residue on a wafer after a CMP process is performed on the wafer.

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

Abstract: A semiconductor device includes a substrate, a chip region in the substrate, a scribe lane region in the substrate, first active patterns in the chip region, a first device isolation pattern on the first active patterns, second active patterns in the scribe lane region, and a second device isolation pattern on the second active patterns. The scribe lane region is adjacent to the chip region. The first device isolation pattern includes a first device isolation material, and the second device isolation pattern includes a second device isolation material. The second device isolation material is different from the first device isolation material.

Abstract: A slurry arm is provided. The slurry arm includes: an arm body; a slurry line that extends through the arm body; an oxygen removal chamber provided in the arm body and configured to receive slurry from the slurry line; a purge gas supplier configured to supply a purge gas to the slurry in the oxygen removal chamber; and a main valve configured to selectively discharge gas from the oxygen removal chamber.

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

Abstract: A semiconductor device includes a lower structure; an intermediate insulating structure on the lower structure; an intermediate interconnection structure penetrating through the intermediate insulating structure; an upper insulating structure on the intermediate insulating structure and the intermediate interconnection structure; and an upper conductive pattern penetrating through the upper insulating structure and electrically connected to the intermediate interconnection structure, wherein the intermediate insulating structure includes an intermediate etch-stop layer and an intermediate insulating layer thereon, the intermediate insulating layer includes first and second intermediate material layers, the second intermediate material layer having an upper surface coplanar with an upper surface of the first intermediate material layer, the intermediate interconnection structure penetrates through the first intermediate material layer and the intermediate etch-stop layer, and a material of the first intermedia

Abstract: A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

Abstract: A semiconductor device including a substrate; a gate structure on the substrate; a gate spacer on a sidewall of the gate structure; and a polishing stop pattern on the gate structure and the gate spacer, the polishing stop pattern including a first portion covering an upper surface of the gate structure and an upper surface of the gate spacer; and a second portion extending from the first portion in a vertical direction substantially perpendicular to an upper surface of the substrate, wherein an upper surface of a central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the first portion thereof, and the upper surface of the central portion of the first portion of the polishing stop pattern is substantially coplanar with an upper surface of the second portion thereof.

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode extending in a second direction and crossing the active pattern, a gate capping pattern covering a top surface of the gate electrode, and a separation structure at a side of the gate electrode and extending in the second direction to penetrate the active pattern in a third direction. The first and second directions are parallel to a bottom surface of the substrate and are perpendicular to the third direction. The separation structure may include a filling pattern, which extends in the third direction to penetrate the active pattern, and a vertical insulating pattern, which is interposed between the filling pattern and the gate electrode. A top surface of the separation structure may be located at a height lower than a top surface of the gate capping pattern.

Abstract: A semiconductor device may include a substrate including a first cell region, a second cell region, and a dummy region between the first and second cell regions, and conductive patterns included in the first cell region, the second cell region, and the dummy region. A first pattern density, which is defined as a density of the conductive patterns of the first cell region, may be different from a second pattern density, which is defined as a density of the conductive patterns of the second cell region. A third pattern density, which is defined as a density of the conductive patterns of the dummy region, gradually changes in a region between the first cell region and the second cell region. A top surface of the substrate may be inclined at an angle, in the dummy region.

Abstract: A semiconductor device manufacturing method is capable of manufacturing a semiconductor device with improved reliability, by simplifying a chemical mechanical polishing (CMP) process and minimizing a thickness distribution of a dummy gate during the CMP process. The semiconductor device manufacturing method includes forming, on a substrate, dummy gate structures extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, each dummy gate structure including a dummy gate and a mask pattern on an upper surface of the dummy gate; forming an interlayer insulating layer covering the dummy gate structures; and performing the single slurry CMP process of removing some of the interlayer insulating layer and the dummy gate structures through the single slurry CMP process and exposing the upper surface of the dummy gate.

Abstract: A substrate cleaning device, includes: a substrate cleaning module including first and second roll members adjacent to lower and upper surfaces of a substrate, respectively, first and second driving units configured to move the first and second roll members, a first roll cleaning module including a roll receiving region, a first cleaning solution supply unit supplying a first cleaning solution, and an ultrasonic generating unit applying ultrasonic vibrations; a second roll cleaning module including a housing, a brush pad in the housing, and a second cleaning solution supply unit supplying a second cleaning solution; and a control unit controlling the first driving unit so that the first roll member contacts the substrate lower surface or is accommodated in the roll receiving region, and to control the second driving unit so that the second roll member contacts the substrate upper surface or is seated on the brush pad.

Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, lower electrodes on the cell region of the substrate, a dielectric layer on surfaces of the lower electrodes, a silicon germanium layer on the dielectric layer, a metal plate pattern and a polishing stop layer pattern stacked on the silicon germanium layer, and upper contact plugs physically contacting an upper surface of the silicon germanium layer. The upper contact plugs may have an upper surface farther away from the substrate than an upper surface of the polishing stop layer pattern. The upper contact plugs may be spaced apart from the metal plate pattern and the polishing stop layer pattern.

Abstract: A semiconductor device may include a substrate, a patterned structure, a filling pattern, and a conductive spacer. The substrate may include a semiconductor chip region and an overlay region. The patterned structure may include bit line structures spaced by a first distance on the semiconductor region, define a first trench and a second trench on first and second regions of the overlay region, and include key structures on the second region and spaced apart by the second trench. The filling pattern may fill lower portions of the first and second trenches on the first and second regions. The first region may be an edge portion of the overlay region. The second region may be a central portion of the overlay region. The conductive spacer may contact an upper surface of the filling pattern and may be on an upper sidewall of each of the first and second trenches.