Patents by Inventor Ilyoung Yoon

Ilyoung Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9006067
    Abstract: A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo Kyeong Kang, Jaeseok Kim, Boun Yoon, Hoyoung Kim, Ilyoung Yoon
  • Publication number: 20140227848
    Abstract: A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.
    Type: Application
    Filed: January 2, 2014
    Publication date: August 14, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bo Kyeong KANG, Jaeseok KIM, Boun YOON, Hoyoung KIM, Ilyoung YOON
  • Publication number: 20140051246
    Abstract: Methods of fabricating a semiconductor device are provided. The methods may include preparing a semiconductor substrate, forming insulating patterns including a trench on the semiconductor substrate, conformally forming a metal layer covering an inner surface of the trench on the insulating patterns, conformally forming a protecting layer on the metal layer, and performing a chemical mechanical polishing (CMP) process on the protecting layer and the metal layer until top surfaces of the insulating patterns are exposed, thereby forming a metal pattern and a protecting pattern in the trench. The CMP process may use a slurry including polishing particles having negative charges.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 20, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chae Lyoung Kim, Ilyoung Yoon, Boun Yoon
  • Publication number: 20110151316
    Abstract: A battery pack including a plurality of battery cells, the battery cells including positive electrode terminals and negative electrode terminals; and a first substrate and a second substrate, the first substrate and second substrate being selectively coupleable to the positive electrode terminals and the negative electrode terminals of the plurality of battery cells, wherein the first substrate includes a first circuit for connecting the positive electrode terminals and the negative electrode terminals to connect the plurality of battery cells together in a first manner, and the second substrate includes a second circuit for electrically connecting the plurality of battery cells in a second manner different from the first manner.
    Type: Application
    Filed: June 24, 2010
    Publication date: June 23, 2011
    Inventor: Ji-Ilyoung Yoon
  • Patent number: 7452817
    Abstract: A chemical mechanical polishing (CMP) method is disclosed for use in the fabrication of a semiconductor device having dense and sparse regions. The method uses an abrasive stop layer formed on the dense and sparse regions to control polishing of a material layer formed on the abrasive stop layer by a rigid, fixed abrasive polishing pad.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: November 18, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ilyoung Yoon, Jae Ouk Choo, JaEung Koo
  • Publication number: 20070167014
    Abstract: A chemical mechanical polishing (CMP) method is disclosed for use in the fabrication of a semiconductor device having dense and sparse regions. The method uses an abrasive stop layer formed on the dense and sparse regions to control polishing of a material layer formed on the abrasive stop layer by a rigid, fixed abrasive polishing pad.
    Type: Application
    Filed: October 5, 2006
    Publication date: July 19, 2007
    Inventors: Ilyoung Yoon, Jae Ouk Choo, JaEung Koo