Abstract: A semiconductor memory circuit includes a memory cell array having a plurality of memory cells. Column selection lines constitute connection lines extending from the memory cell array and are divided into hierarchies like a tree by selecting transistors. More specifically, a column selection system is hierarchically divided into column selection lines belonging to a first-stage column decoder and a second-stage column decoder. Row selection lines are controlled by a row decoder. The semiconductor memory circuit also includes an ATD circuit for detecting a transition of an address signal to generate a pulse, a pulse width control circuit for controlling the width of the pulse to determine data in a sense amplifier, and a latch circuit for latching readout data in response to the width of the pulse. A delay circuit is provided in the first-stage column decoder of an upper hierarchy to which a small number of selecting transistors belong and from which a signal rises at high speed.