Abstract: A system for designing a digital circuit including: a digital circuit simulator based on a file containing a functional description of the digital circuit; a mechanism estimating an output variable from the digital circuit when executing a test bench supplied to the simulator; event counters, events being detected using control signals provided by the simulator when executing the test bench; and a mechanism building at least one calculation model of the digital circuit output variable based on a sequence of estimation data of the output variable and output data of the event counters. The building mechanism can assign a plurality of possible modes to the output variable and build a different output variable calculation model for each possible mode.

Abstract: A system for designing digital circuitry comprising: a digital circuit simulator based on a file containing a functional description of this digital circuit; means for estimating an output variable from the digital circuit when executing a test bench supplied to the simulator; event counters, the events being detected using control signals provided by the simulator when executing the test bench. Said system further comprises means for selecting a portion of the event counters by iteratively optimizing a model for calculating the output variable of the digital circuit using output data from the event counters and means for registering the selected portion of event counters and the optimized calculation model.