Abstract: A method of transmitting timing critical data via an asynchronous channel without changing any datum to be transmitted. The timing critical data can be an MPEG transport stream. The asynchronous channel can be a computer or telephone network, a digital storage media such as a digital VCR, or a digital interface. The method involves tagging each transmission unit of the data stream, before inputting to the channel, with timing information, and using the timing information at the output end of the channel to recreate the proper data timing, Various schemes are described for packing the timing information tags with each or a plurality of transmission units.

Abstract: During recording of an MPEG information signal on a record carrier (40), transport packets (P.sub.k) are stored in signal blocks in a track (1) on the record carrier (40). x transport packets of the MPEG information signal are stored in the second block sections (SB) of y signal blocks, where x and y are integers, x.gtoreq.1 and y>1, more specifically, y>x. Further, third block sections (TB) are present in one or more of the second block sections in the y signal blocks of a group for storing additional information, which additional information relates to the specific application of recording and reproducing the MPEG information signal on/from the record carrier.

Abstract: A method of transmitting timing critical data via an asynchronous channel. The timing critical data can be an MPEG transport stream of packets. The asynchronous channel can be a computer or telephone network, a digital storage media such as a digital VCR, or a digital interface. The packets are processed serially through a remuxer to obtain a constant rate and delivered to and consumed by one or more target decoders, for example, inside a TV set or in a set-top decoder. To prevent overflow of the transport buffers inside these decoders, a single monitor-scheduler is provided which monitors the transport buffers and delivers to each the packets wanted scheduled so as to avoid buffer overflow and loss of information. The method also includes restamping the transport packets with new PCRs. The remuxing scheme is simple enough to implement on DVCR or other consumer applications.

Abstract: Device for splitting an interlaced television frame into a vertical low-frequency spatial signal and a vertical high-frequency motion auxiliary signal. In a forward play mode the two signals are added together. In a reverse play mode, in which the frames are supplied in the reverse order, the motion auxiliary signal is subtracted from the spatial signal.

Abstract: A hashing data storage and retrieval arrangement whose storage capacity is unaffected by collisions. A first memory serves as a hash index table, for storing pointers at each address location corresponding to a hash value generated by hashing a key data word. Each pointer is the address of a location in a second memory, which has a separate storage location for each key data word, its associated data, and a further pointer which is the address of the next key data word resulting from a collision during hashing. Preferably a pipeline register between the two memories permits hashing of a subsequent key data word while accessing of the second memory is still in progress.

Abstract: Device for splitting a digital interlaced television signal into components in which interlaced frames are applied to a vertical low-pass filter (6). To prevent motion artefacts in the spatial signal thus obtained, the interlaced frame is also applied to a vertical high-pass filter (8). This vertical high-pass filter supplies a motion auxiliary signal which may have a small vertical bandwidth. When combining the spatial signal and the motion auxiliary signal, noticeable motion artefacts do not occur in the interlaced frame. The device may be used for deriving a standard television signal from a high-definition television (HDTV) signal and for compatible transmission of HDTV signals.

Abstract: A decoder for data encoded in a form combining a prefix which is a previously coded sub-string and a next data element in the data stream. The decoder includes memories for storing code words and data separately. Upon receipt of a code word the decoder stores the previously received code word, applies the newly received word to the code word memory to obtain the location of the last data element which is part of the data represented by the newly received code word, and another code word associated with the prefix. Upon completion of decoding the latest code word, the first data element of the decoded word is appended to the next previously received code word, and the combination is stored as the equivalent of a code word which is next after the highest code word already received. At least one memory is shared for use during encoding and decoding.

Abstract: A digital multiplier circuit which implements a modified multiplier algorithm in binary form and can be implemented as a very large scale integrated circuit. The modified algorithm replaces the large summation required in a typical shift-and-add digital multiplier with the sum of smaller summation terms, both yielding the same product. The digital word representing one of the multiplicands is partitioned or sliced into groups of two or more bits. All possible values of each bit slice are pre-calculated and stored to derive partial products thereof by the other multiplicand. The summation of such partial products rather than of individual bit products reduces the number of partial adders by half or more, depending on the number of bits in each partition or slice.

Abstract: A digital transversal filter which employs a multiplierless algorithm for effecting convolutions of samples of a digital input word by the filter coefficients. Each of the samples of an input word is bit sliced into segments of two or more bits, and convolutions are carried out in parallel on all segments using only adders and registers. The convolution products are then summed in a pipeline adder tree to derive the convolution of the complete input word. This architecture provides high frequency capability and significantly lower transistor count and hardware complexity, enabling efficient very large scale integration (VLSI) implementation.

Abstract: An architecture for a very large scale integrated (VLSI) implementation of a finite imprise response (FIR) digital filter having no multipliers and a coefficient space limited to powers of two. The filter structure includes a data bus, a coefficient bus and a sum-in bus to each coefficient tap. Each tap has a coefficient and control word register which is loaded during an initialization phase of the filter. Multiplication is provided by a shifter which provides the correct power of two weighting of an input data sample. The weighted data sample at each tap is added to the output of the previous tap. This architecture results in a regular, modular structure which can be cascaded and which is programmable for various data word lengths and coefficient spaces.