Abstract: Clock supply for multiplex systems for distributing at least one system clock signal and at least one frame clock signal, whereby a marking circuit is provided to which both clock signals are provided and that generates a combined system-frame clock signal by marking the system clock signal. This combined system-frame clock signal is transmitted on a single clock line and being separated in turn into the system clock signal and the frame clock signal by a separating circuit.

Abstract: A method and apparatus for equalizing pulse widths of a digital signal. In digital communications transmission systems, the transmitted digital signals are regenerated using line equalizers. Since higher requirements exist for the equalization with digital clock recovery equipment, it is necessary to again equalize the pulse widths. The beginning of the pulses of the equalized digital signal (D3) is obtained from the leading edges of the pulses of the digital signal (D2) which is to be equalized and the end of the pulses of the equalized digital signal (D3) is obtained from the leading edges of the pulses of an auxiliary data clock (DHT). The equipment can be an integrated circuit which has two D-flipflops (22, 23) that alternately process the pulses under the control of a JK-flipflop (26). Digital signals (D2) having a bit rate equal to or greater than 34Mbit/s can also be processed.

Abstract: A circuit arrangement has a control logic stage, a clock monitoring stage, and a clock selector stage. The control logic stage includes a shift register having register cells that are identical with the exception of the first. The identical shift registers have a D-flip-flop in which a pre-control signal is formed by intermediate storage of a control signal. A pre-control signal arises in the first register cell when all other pre-control signals are absent. The switching ensues dependent on a correction signal and the clocks at the affected registered cells such that the previous control signal is first disconnected before the new control signal is engaged. In the clock selector stage, the active control signal through-connects the allocated clock as auxiliary data clock. The clock monitoring stage generates a start signal when either no control signal is present or when a plurality of control signals were erroneously formed at the same time.

Abstract: A working/standby clock pulse supply for digital systems, particularly for synchronous multiplex systems and switching systems, has a working clock oscillator and a standby oscillator. The working clock signal or the standby clock signal is guided by way of assemblies whereby at least one clock signal summing circuit is provided which adds equal harmonic spectral signals of various amplitudes of the working clock signal and the standby clock signal to provide a resulting spectral signal.

Abstract: A method and arrangement for generating a correction signal for a digital clock recovery circuit. This method cost effectively provides phase sensors that can be realized in integrated technology. In a sample-and-hold circuit, an auxiliary data clock (DHT1) that is valid as a recovered clock of a digital signal (DS1) and whose clock frequency is somewhat higher or lower than the bit rate of this digital signal (DS1) is sampled by the latter. Then a trailing edge of a pulse of this auxiliary data clock (DHT1) is identified by a status change. The sample-and-hold circuit then outputs a correction request signal (K1) that releases a correction signal (K) in a following circuit, this correction signal (K) being synchronous with the auxiliary data clock (DHT1). This method is utilized in digital clock recovery equipment.

Abstract: A digital clock recovery system according to the prior art contains a phase sensor with a delay device. This cannot be implemented with the required accuracy in integrated circuit technology. The invention does not required any delay device for its implementation. A phase sensor (6) does not compare the phase relationship of the active edges of the pulses of a digital signal (DS) with a first auxiliary data clock (DHT1) which acts as clock recovered from the digital signal (DS), but instead, at phase sensor (6) compares the phase relationship of the active edges of the pulses of the digital signal (DS) and a second auxiliary data clock (DHT2) which has a defined phase difference relative to the first auxiliary data clock (DHT1). If the comparison does not result in a phase difference, a correction signal (K) is generated which causes a phase correction of both of the auxiliary data clocks (DHT1, DHT2) which produce the defined phase difference.