Abstract: Disclosed are a semiconductor device (1) including a MOSPET region and an integrated diode region, and a manufacturing method thereof. More particularly, a semiconductor device (1) including a silicon carbide (SiC) MOSPET region and an integrated Schottky bather diode that reduce forward voltage drop (Vf), device area, and switching oscillation resulting from parasitic inductance are disclosed.

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: A display device comprises a substrate, a semiconductor layer thereon, a first insulating layer on the semiconductor layer, a first conductive layer on the first insulating layer and including a first electrode pattern, a second insulating layer on the first insulating layer and including first and second conductive patterns, a third insulating layer on the second conductive layer, and a display element layer on the third insulating layer and including a first pixel electrode connected to the first conductive pattern through a first via hole, a second pixel electrode connected to the second conductive pattern through a second via hole, and a micro light-emitting element between the pixel electrodes, the first conductive pattern contacting the semiconductor layer through a first contact hole and the first electrode pattern through a second contact hole, and the second conductive pattern overlapping the first electrode pattern to form a first capacitor therewith.

Abstract: A display device includes pixels disposed in a display area and including first and second pixels that are adjacent to each other in a first direction, and a first integrated bank pattern disposed between the first and second pixels. Each of the pixels includes a first electrode and a second electrode that are spaced apart from each other along the first direction in a light emitting area and extend in a second direction, a first bank pattern portion overlapping the first electrode, and a second bank pattern portion overlapping the second electrode. The first integrated bank pattern includes a second bank pattern portion disposed at the first pixel, a first bank pattern portion disposed at the second pixel, and a protrusion extending in the second direction in a boundary area between the first pixel and the second pixel.

Abstract: An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.

Abstract: A semiconductor device may include a first film and a second film defining parts of a trench, a plug conductive film, a via, and a wiring in the trench. The trench may include a second sub-trench having a second width below a first sub-trench having a first width. The plug conductive film may extend from a first side of the first film to penetrate a bottom face of the trench. An uppermost face of the plug conducive film may be in the trench. The via may include an insulating liner between the plug conductive film and the first film. The uppermost face of the plug conductive film and at least a part of a side wall of the plug conductive film may be in contact with the wiring. An upper face of the insulating liner may be exposed by a bottom face of the second sub-trench.

Abstract: A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a plurality of pads disposed on the first insulating layer and having top surfaces exposed through the cavity; wherein the cavity of the second insulating layer includes: a bottom surface positioned higher than a top surface of the first insulating layer; and an inner wall extending from the bottom surface, wherein the inner wall is perpendicular to top or bottom surface of the second insulating layer, wherein the bottom surface of the cavity includes: a first bottom surface positioned lower than a top surface of the pad and positioned outside an arrangement region of the plurality of pads; and a second bottom surface positioned lower than the top surface of the pad and positioned inside the arrangement region of the plurality of pads, and wherein a height of the first bottom surface is different from a height of the second bottom surface.

Abstract: An electronic device according to various embodiments of the present invention may comprise: a housing comprising a first surface facing in a first direction and a second surface facing in a second direction that is opposite to the first direction, the first surface comprising an at least partially transparent part and at least one opening formed adjacent to the at least partially transparent part; a camera positioned inside the housing, the camera comprising an image sensor facing in the first direction through the at least partially transparent part of the housing; and an acoustic component arranged between the first surface and the second surface, the acoustic component comprising a vibration plate configured to generate a sound such that the same moves in at least one direction selected from the first and second directions, a first passage formed in a third direction that is substantially perpendicular to the first direction such that the generated sound passes through the same, and a second passage forme

Abstract: A display device includes first and second electrodes, light-emitting elements on the first and second electrodes, data lines extending from a pad area to a display area, connection wirings spaced apart from the data lines and extending from the pad area to a non-display area on respective sides of the display area, first pads overlapping the data lines in the pad area, and second pads overlapping the connection wirings, wherein the connection wirings include a first connection wiring overlapping a second pad, a second connection wiring not overlapping the second pad and overlapping the first connection wiring in the non-display area, and a third connection wiring overlapping the first connection wiring and electrically connected to the second pad, wherein the first and third connection wirings overlap each other in the pad area, and the first, second, and third connection wirings overlap each other in the non-display area.

Abstract: An inductor includes a first magnetic body having a toroidal shape and having a ferrite; and a second magnetic body configured to be different from the first magnetic body and including a metal ribbon, wherein the second magnetic body includes an outer magnetic body disposed on an outer circumferential surface of the first magnetic body and an inner magnetic body disposed on an inner circumferential surface of the first magnetic body, and each of the outer magnetic body and inner magnetic body is wound in a plurality of layers in a circumferential direction of the first magnetic body.

Abstract: A micro electrode array (MEA) platform including a cell culture container configured to accommodate a cell culture medium to culture neurons, an MEA including an electrode configured to sense the neurons, and a temperature control device configured to control a transfer of heat generated by a heating source through a heating wire, based on whether a temperature of the cell culture medium or the electrode is equal to a reference temperature for the neurons.

Abstract: An apparatus for automatically inspecting the welding state of a battery module is configured to inspect welding states of welding parts of a plurality of leads for electrical connection based on a deep penetration inspection using application of eddy current to the welding parts of the leads.

Abstract: The present invention relates to a method for manufacturing a non-oriented electrical steel sheet, and a non-oriented electrical steel sheet manufactured thereby, and the method for manufacturing a non-oriented electrical steel sheet, according to the present invention, comprises the steps of: (a) reheating a steel slab comprising 0.05 wt % or less of C, 1.0-3.5 wt % of Si, 0.2-0.6 wt % of Al, 0.02-0.20 wt % of Mn, 0.01-0.20 wt % of P, 0.01 wt % or less of S, and the balance of Fe and inevitable impurities, and then performing hot rolling on same; (b) performing hot rolling annealing heat-treatment and pickling on a hot rolled steel sheet; (c) performing cold rolling on the pickled steel sheet; (d) performing insulation coating on the cold rolled steel sheet, and then processing same; and (e) performing final heat treatment by heating, soaking and cooling the processed steel sheet, wherein soaking process is maintained and carried out at a temperature of 850° C.

Abstract: An object of the present disclosure is to implement a coloring pattern with a low moisture content on an electrode substrate to thereby improve display reliability and lifetime as well as vivid colors. That is, since when the moisture content is 50 ppm or more, it may cause a reduction in luminance and lifetime due to pixel shrinkage, in order to minimize the moisture content after completion of the post-baking process, the generation of moisture in the panel state is minimized by generating sufficient heat and time in the post-baking step, by including the colorant of the present disclosure.

Abstract: Provided is a method for recovering and reusing an active material from a positive electrode scrap.

Abstract: A method (480, 580) of depositing layers of a thin-film transistor on a substrate using a sputter deposition source comprising at least one first pair of electrodes and at least one second pair of electrodes, the method comprising moving (482, 582) the substrate to a first vacuum chamber; depositing (484, 584) a first layer of the layers on the substrate by supplying the at least one first pair of electrodes with bipolar pulsed DC voltage, wherein a first material of the first layer comprises a first metal oxide; moving (486, 586) the substrate from the first vacuum chamber to a second vacuum chamber without a vacuum break; and depositing (488, 588) a second layer of the layers on the first layer by supplying the at least one second pair of electrodes with bipolar pulsed DC voltage, wherein a second material of the second layer comprises a second metal oxide, the second material being different from the first material.

Abstract: the present invention relates to a magnetic mixer to which a disposable resin liquid pouch is applied instead of a metal tank, for accommodating and mixing liquids therein, to minimize cross-contamination of liquids to be mixed due to an unwashed residue, increase a magnetic coupling force between rotors for driving an impeller inside the liquid pouch and an impeller outside the liquid pouch by a magnetic coupling method, and prevent separation of the impeller in liquids to be mixed, and a magnetic mixing system.

Abstract: A method of manufacturing a multilayer metal plate by electroplating includes a first forming operation of forming one of a first metal layer and a second metal layer on a substrate by electroplating, wherein the second metal layer is less recrystallized than the first metal layer, the second metal layer is comprised of nanometer-size grains, and the second metal layer has a higher level of tensile strength than the first metal layer; and a second forming operation of forming, by electroplating, a third metal layer not formed in the first forming operation on a surface of one of the first metal layer and the second metal layer formed in the first forming operation.

Abstract: A display device includes a light-emitting diode including a first conductivity-type semiconductor, an active layer, and a second conductivity-type semiconductor; a first voltage line to which a first voltage is applied; a second voltage line to which a second voltage is applied; a first transistor including a source electrode electrically connected to the first voltage line and a drain electrode electrically connected to a first electrode of the light-emitting diode and to the first conductivity-type semiconductor; a second transistor including a drain electrode electrically connected to a gate electrode of the first transistor and a source electrode electrically connected to a data line to apply a data signal; a capacitor electrically connected to the gate electrode of the first transistor and the first electrode; and a third transistor including a source electrode electrically connected to the second voltage line and a drain electrode electrically connected to the first electrode.

Abstract: An object of the present disclosure is to improve display reliability and lifetime as well as vivid colors. When there remain residues in the washing part due to incomplete removal during the developing step, it can cause dark spots or pixel off due to the residues, and thus residue-free pixels can be formed by optimizing the temperature and time for developing. Additionally, when the amount of outgas in the panel after post-baking is 15 ppm or more, it may cause a reduction in luminance and lifetime due to pixel shrinkage. Therefore, in order to minimize the amount of outgas after completion of the post-baking process, the generation of outgas in the panel state can be minimized by generating sufficient fume in the post-baking step, in addition to forming clean pixels in the developing step.