Abstract: A sensing device includes a light-transmissible substrate, a light-transmissible electrode unit connected thereto, including multiple electrically independent electrode lines, and a light sensing unit connected to the light-transmissible substrate and the light-transmissible electrode unit. The light sensing unit includes a plurality of light sensors for sensing a light transmitted from the light-transmissible substrate. The light sensors are confined within the light-transmissible electrode unit and are electrically connectable to an outer component through the light-transmissible electrode unit.

Abstract: A sensing device includes a light-transmissible substrate, a light-transmissible electrode unit connected thereto, including multiple electrically independent electrode lines, and a light sensing unit connected to the light-transmissible substrate and the light-transmissible electrode unit. The light sensing unit includes a plurality of light sensors for sensing a light transmitted from the light-transmissible substrate. The light sensors are confined within the light-transmissible electrode unit and are electrically connectable to an outer component through the light-transmissible electrode unit.

Abstract: Disclosed are methods for processing distribution channel data integrating business information with geographic data to produce integrated data, wherein the integrated data has greater resolution than the business information. Distribution channel data is captured and correlated with the integrated data to increase the resolution of the distribution channel data.

Abstract: Disclosed are methods for processing distribution channel data integrating business information with geographic data to produce integrated data, wherein the integrated data has greater resolution than the business information. Distribution channel data is captured and correlated with the integrated data to increase the resolution of the distribution channel data.

Abstract: A CMOS process for double vertical channel thin film transistor (DVC TFT). This process fabricates a CMOS with a double vertical channel (DVC) structure and defines the channel without an additional mask. The DVC structure of the CMOS side steps the photolithography limitation because the deep-submicrometer channel length is determined by the thickness of gate, thereby decreasing the channel length of the CMOS substantially.

Abstract: A CMOS process for double vertical channel thin film transistor (DVC TFT). This process fabricates a CMOS with a double vertical channel (DVC) structure and defines the channel without an additional mask. The DVC structure of the CMOS side steps the photolithography limitation because the deep-submicrometer-channel length is determined by the thickness of gate, thereby decreasing the channel length of the CMOS substantially.

Abstract: A CMOS process for double vertical channel thin film transistor (DVC TFT). This process fabricates a CMOS with a double vertical channel (DVC) structure and defines the channel without an additional mask. The DVC structure of the CMOS side steps the photolithography limitation because the deep-submicrometer channel length is determined by the thickness of gate, thereby decreasing the channel length of the CMOS substantially.

Abstract: A method for manufacturing an LCD panel comprises the steps of providing a substrate having a conducting layer forming a pad and a conducting line, and an isolation layer on the pad and the conducting line, forming a planarization layer on the isolation layer above the conducting line, and a first through hole in the planarization layer, the first through hole exposing the isolation layer and aligned with the conducting line, forming a masking layer on the isolation layer above the pad, and a second through hole in the masking layer, the second through hole exposing the isolation layer and aligned with the pad, and etching the isolation layer with the masking of the planarization layer and the masking layer, whereby the isolation layer exposed by the first and second through hole is removed.

Abstract: A process for forming a thin film transistor includes steps of (a) forming a gate on a portion of a substrate, (b) forming a gate dielectric layer, a semiconductor layer, a source, a drain, and a passivation in order on the substrate, and (c) proceeding a thermal treatment under atmosphere of a specific assistant gas. The specific assistant gas is one selected from a group consisting of hydrogen, steam, inert gases, and gas mixtures thereof. After providing the specific assistant gas during the thermal treatment, the process can improve the output property of the thin film transistor for avoiding double hump phenomenon.

Abstract: A CMOS process for double vertical channel thin film transistor (DVC TFT). This process fabricates a CMOS with a double vertical channel (DVC) structure and defines the channel without an additional mask. The DVC structure of the CMOS side steps the photolithography limitation because the deep-submicrometer channel length is determined by the thickness of gate, thereby decreasing the channel length of the CMOS substantially.

Abstract: A double vertical channel thin film transistor (DVC TFT) for static random access memory (SRAM) and method of making the same is disclosed. The DVC TFT of the present invention has a double vertical channel structure, this channel structure side steps the photolithography limitation because the deep-submicrometer channel length is determined by the thickness of gate, thereby decreasing the channel length substantially.

Abstract: A method for manufacturing an LCD panel comprises the steps of providing a substrate having a conducting layer forming a pad and a conducting line, and an isolation layer on the pad and the conducting line, forming a planarization layer on the isolation layer above the conducting line, and a first through hole in the planarization layer, the first through hole exposing the isolation layer and aligned with the conducting line, forming a masking layer on the isolation layer above the pad, and a second through hole in the masking layer, the second through hole exposing the isolation layer and aligned with the pad, and etching the isolation layer with the masking of the planarization layer and the masking layer, whereby the isolation layer exposed by the first and second through hole is removed.

Abstract: A method of patterning an indium tin oxide (ITO) layer is performed on a glass substrate. First, using sputtering, an amorphous ITO layer is deposited on the glass substrate. Then, using excimer laser annealing (ELA), the amorphous ITO layer within a predetermined pattern is turned into a crystalline ITO layer. Finally, using an etch solution, the amorphous ITO layer outside the predetermine pattern is removed.

Abstract: A process for forming a thin film transistor includes steps of (a) forming a gate on a portion of a substrate, (b) forming a gate dielectric layer, a semiconductor layer, a source, a drain, and a passivation in order on the substrate, and (c) proceeding a thermal treatment under atmosphere of a specific assistant gas. The specific assistant gas is one selected from a group consisting of hydrogen, steam, inert gases, and gas mixtures thereof. After providing the specific assistant gas during the thermal treatment, the process can improve the output property of the thin film transistor for avoiding double hump phenomenon.

Abstract: A method of patterning an indium tin oxide (ITO) layer is performed on a glass substrate. First, using sputtering, an amorphous ITO layer is deposited on the glass substrate. Then, using excimer laser annealing (ELA), the amorphous ITO layer within a predetermined pattern is turned into a crystalline ITO layer. Finally, using an etch solution, the amorphous ITO layer outside the predetermine pattern is removed.

Abstract: A method and resulting structure is described for fabricating a thin film transistor which very effectively uses ITO as its transparent electrode. The method begins by providing a suitable substrate and forming thereover a polysilicon layer. A gate insulator layer is formed upon the polysilicon layer. A gate electrode layer is formed over the gate insulator layer. The gate electrode and gate insulator layers are then patterned to leave the desired gate insulator and gate electrode for the thin film transistor. An insulating layer is formed over the top surface of the structure. The isolating layer is patterned to provide openings to the designated source/drain regions of the thin film transistor. A conductive layer is deposited to make electrical contact to the source/drain regions of the thin film transistor. A silicon nitride passivation layer is formed over the conductive layer. The silicon nitride passivation layer is patterned to leave portions of the conductive layer open.