Patents by Inventor In Chang

In Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176901
    Abstract: The present disclosure discloses a simulating interface system, which is assembled with an electronic device and has an interface module and a simulating module. The interface module is connected with an external electronic device, and receives connection signals from the external electronic device; and the simulating module is connected with the interface module, and has a simulating unit and a management unit, wherein the simulating unit is used to simulate a use authority of the electronic device, and the management unit adjusts the use authority to provide to the external electronic device based on the connection signals. The simulating unit analogizes the use authority of the electronic device, and the management unit adjusts the use authority to provide to the external electronic device based on the connection signals from the external electronic device, so as to achieve effective protection.
    Type: Application
    Filed: November 24, 2023
    Publication date: May 30, 2024
    Applicant: Lanto Electronic Limited
    Inventors: Chih-Hsiung CHANG, Chih-Wei SUN, Chia-Ching LIN
  • Publication number: 20240178076
    Abstract: A method includes providing a first substrate which has an active layer, a metal layer, a passivation layer disposed on the metal layer, a first patterned metal layer passing through the passivation layer to electrically connected to the active layer, an insulating layer disposed on the passivation layer, and a second patterned metal layer passing through the insulating layer to electrically connected to the first patterned metal layer. A part of the metal layer does not serve as a portion of a thin film transistor, but serves as a portion of a gate line. The method includes providing a second substrate supporting a plurality of elements, transferring at least one of the plurality of elements from the second substrate to the second patterned metal layer of the first substrate, and fixing the at least one of the plurality of elements to the first substrate.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 30, 2024
    Inventors: Chia-Hsiung CHANG, Ting-Kai HUNG, Hsiao-Lang LIN
  • Publication number: 20240177319
    Abstract: Many unsupervised domain adaptation (UDA) methods have been proposed to bridge the domain gap by utilizing domain invariant information. Most approaches have chosen depth as such information and achieved remarkable successes. Despite their effectiveness, using depth as domain invariant information in UDA tasks may lead to multiple issues, such as excessively high extraction costs and difficulties in achieving a reliable prediction quality. As a result, we introduce Edge Learning based Domain Adaptation (ELDA), a framework which incorporates edge information into its training process to serve as a type of domain invariant information. Our experiments quantitatively and qualitatively demonstrate that the incorporation of edge information is indeed beneficial and effective, and enables ELDA to outperform the contemporary state-of-the-art methods on two commonly adopted benchmarks for semantic segmentation based UDA tasks.
    Type: Application
    Filed: November 24, 2023
    Publication date: May 30, 2024
    Applicant: MEDIATEK INC.
    Inventors: Ting-Hsuan Liao, Huang-Ru Liao, Shan-Ya Yang, Jie-En Yao, Li-Yuan Tsao, Hsu-Shen Liu, Bo-Wun Cheng, Chen-Hao Chao, Chia-Che Chang, Yi-Chen Lo, Chun-Yi Lee
  • Publication number: 20240178620
    Abstract: An electrical connector comprises an outer housing, an insulating housing installed on the outer housing, a pair of terminal assemblies, and a shielding member. The terminal assemblies are installed in the insulating housing and are spaced apart from each other in a first direction to define an insertion space therebetween adapted to receive a connection terminal of a mating connector. Each terminal assembly includes a plurality of conductive terminals arranged in rows in a second direction perpendicular to the first direction. The plurality of conductive terminals of each terminal assembly include a signal terminal and a ground terminal. The shielding member is positioned at least partially between the two terminal assemblies in the first direction and includes a contact arm in electrical contact with the ground terminal.
    Type: Application
    Filed: November 30, 2023
    Publication date: May 30, 2024
    Applicants: Tyco Electronics Holdings (Bermuda) No. 7 Limited, Tyco Electronics (Shanghai) Co., Ltd.
    Inventors: Lizhou (Leo) Li, Xinjie (David) Zhang, Kehao (Asroc) Chen, Ching Hsiang Chang
  • Publication number: 20240177504
    Abstract: The single cell identification described herein utilizes cell image information and extracts cell features with a neural network model to subtly distinguish the noise events from single cells, allowing the user to choose which different types of noise events to exclude depending on the requirement of applications. The fast neural network model is able to extract more abundant and specific cell features than handpicked features, which enables the model to be equipped with higher accuracy and higher discriminative capability of distinguishing noise events and identifying the single cells in real-time. Utilization of a neural network model for real-time single cell identification represents a novel technique never applied before. It allows high discriminative capability and high accuracy compared to traditional FACS (Fluorescence-activated Cell Sorting).
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventors: Haipeng Tang, Michael Zordan, Ming-Chang Liu
  • Publication number: 20240178285
    Abstract: A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate. A source electrode, a gate electrode and a drain electrode are disposed on the semiconductor channel layer. A patterned dielectric layer is disposed on the semiconductor barrier layer, and between the gate electrode and the drain electrode. A first field plate is extended continuously from a side of the patterned dielectric layer to the top surface thereof, and has a step in height. A first dielectric layer is disposed between the semiconductor barrier layer and the patterned dielectric layer. A second dielectric layer covers the patterned dielectric layer. The dielectric constant of the patterned dielectric layer is higher than that of the first dielectric layer and the second dielectric layer.
    Type: Application
    Filed: January 16, 2023
    Publication date: May 30, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yi-Wei Lien, Wei-Chih Cheng, Shyh-Chiang Shen, Hsin-Chang Tsai
  • Publication number: 20240177887
    Abstract: A core wire includes: an inner conductor; and an insulating layer covering the inner conductor, wherein the insulation layer is made by 3D printing process, the insulating layer includes a first semi-insulating layer and a second semi-insulating layer, each of the first semi-insulating layer and the second semi-insulating layer has a groove that matchingly accommodates the shape of the inner conductor, and the first semi-insulating layer and the second semi-insulating layer are combined together.
    Type: Application
    Filed: November 25, 2023
    Publication date: May 30, 2024
    Applicant: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: CHUN-LIN LEE, Jian-Guo Cai, Juan Zheng, Lu-Yu Chang
  • Publication number: 20240178319
    Abstract: A semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity. A first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 30, 2024
    Inventors: Hsiang-Pi Chang, Yen-Tien Tung, Dawei Heh, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Tzer-Min Shen, Huang-Lin Chao
  • Publication number: 20240176093
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Publication number: 20240178328
    Abstract: Embodiments include a Schottky barrier diode (SBD) structure and method of forming the same, the SBD structure including a current blockage feature to inhibit current from leaking at an interface with a shallow trench isolation regions surrounding an anode region of the SBD structure.
    Type: Application
    Filed: May 1, 2023
    Publication date: May 30, 2024
    Inventors: Cheng-Hsien Wu, Chien-Lin Tseng, Sheng Yu Lin, Ting-Chang Chang, Yung-Fang Tan, Yu-Fa Tu, Wei-Chun Hung
  • Publication number: 20240178300
    Abstract: A device includes a semiconductor fin semiconductor fin extending from a substrate, a gate structure extending across the semiconductor fin, and a multilayer gate spacer on a sidewall of the gate structure. The multilayer gate spacer includes an inner spacer layer, an outer spacer layer, and a dielectric structure. The inner spacer layer has a vertical portion extending along the sidewall of the gate structure, and a lateral portion laterally extending from the vertical portion in a direction away from the gate structure. The outer spacer layer is spaced apart from the vertical portion of the inner spacer layer by an air gap. The dielectric structure spaces apart a bottom end of the outer spacer layer from the lateral portion of the inner spacer layer.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin CHEN, Che-Cheng CHANG, Chih-Han LIN
  • Publication number: 20240177775
    Abstract: The present technology relates to an electronic device. A memory device including a plurality of memory cells connected to a plurality of word lines arranged between a plurality of source select lines and a plurality of drain select lines, a peripheral circuit configured to perform a program operation of programming data in selected memory cells among the plurality of memory cells, and a program operation controller configured to control the peripheral circuit to apply a voltage, for turning on or off source select transistors connected to the plurality of source select lines, to the plurality of source select lines, while applying a pass voltage to the plurality of word lines after applying a program voltage to selected word lines connected to the selected memory cells.
    Type: Application
    Filed: April 18, 2023
    Publication date: May 30, 2024
    Applicant: SK hynix Inc.
    Inventors: Jae Hyeon SHIN, Chang Han SON, In Gon YANG, Sung Hyun HWANG
  • Publication number: 20240179320
    Abstract: An image encoding/decoding method is provided. An image decoding method of the present invention may comprise deriving an intra-prediction mode of a current luma block, deriving an intra-prediction mode of a current chroma block based on the intra-prediction mode of the current luma block, generating a prediction block of the current chroma block based on the intra-prediction mode of the current chroma block, and the deriving of an intra-prediction mode of a current chroma block may comprise determining whether or not CCLM (Cross-Component Linear Mode) can be performed for the current chroma block.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 30, 2024
    Inventors: Sung Chang LIM, Jung Won KANG, Ha Hyun LEE, Jin Ho LEE, Hui Yong KIM, Yung Lyul LEE, Ji Yeon JUNG, Nam Uk KIM, Myung Jun KIM, Yang Woo KIM, Dae Yeon KIM, Jae Gon KIM, Do Hyeon PARK
  • Publication number: 20240179800
    Abstract: In a first aspect, a communication method is used in a mobile communication system for supporting a multicast and broadcast service (MBS). The communication method includes: determining, by a user equipment having started reception of an MBS session from a base station, whether a predetermined condition is satisfied indicating that the reception has started midway of the MBS session; and transmitting, by the user equipment to the base station lost packet identification information indicating a lost packet group from a start of the MBS session until a start of the reception, when determining that the predetermined condition is satisfied.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Applicant: KYOCERA Corporation
    Inventors: Masato FUJISHIRO, Henry CHANG
  • Publication number: 20240178309
    Abstract: A semiconductor device includes a high electron mobility transistor (HEMT) disposed in an annular active element region, and a resistor disposed in a passive element region surrounded by the annular active element region. The HEM includes a first portion of a compound semiconductor barrier layer stacked on a first portion of a compound semiconductor channel layer. A source electrode, a gate electrode, and a drain electrode are disposed on the first portion of the compound semiconductor barrier layer. The resistor includes a second portion of the compound semiconductor barrier layer stacked on a second portion of the compound semiconductor channel layer. An input terminal electrode is disposed on the second portion of the compound semiconductor barrier layer and located at the center of the passive element region.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Li-Fan Chen, Shao-Chang Huang, Jian-Hsing Lee
  • Publication number: 20240178569
    Abstract: A mobile device supporting wideband operations includes a first metal mechanism element, a dielectric substrate, a feeding radiation element, a ground element, a second metal mechanism element, and a nonconductive antenna window. The first metal mechanism element includes a main portion and a sidewall portion. The sidewall portion has a slot. The dielectric substrate is adjacent to the sidewall portion of the first metal mechanism element. The feeding radiation element extends across the slot of the first metal mechanism element. An antenna structure is formed by the slot of the first metal mechanism element, the dielectric substrate, the feeding radiation element, and the ground element. The second metal mechanism element is disposed opposite from the main portion of the first metal mechanism element. The nonconductive antenna window is connected between the sidewall portion of the first metal mechanism element and the second metal mechanism element.
    Type: Application
    Filed: February 8, 2023
    Publication date: May 30, 2024
    Inventors: Kun-Sheng CHANG, Ching-Chi LIN
  • Publication number: 20240178201
    Abstract: A light-emitting element ink, a display device, and a method of fabricating the display device are provided. The light-emitting element ink includes a light-emitting element solvent, light-emitting elements dispersed in the light-emitting element solvent, each of the light-emitting elements including a plurality of semiconductor layers and an insulating film that surrounds parts of outer surfaces of the semiconductor layers, and a surfactant dispersed in the light-emitting element solvent, the surfactant including a fluorine-based and/or a silicon-based surfactant.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Jun Bo SIM, Duk Ki KIM, Yong Hwi KIM, Hyo Jin KO, Chang Hee LEE, Chan Woo JOO, Jae Kook HA, Na Mi HONG
  • Publication number: 20240178498
    Abstract: A cabinet for receiving an energy storage apparatus includes a substantially cube-shaped frame and a plurality of sheet-shaped concrete structures attached to the frame. The sheet-shaped concrete structure includes an ultra-high performance concrete (UHPC).
    Type: Application
    Filed: October 17, 2023
    Publication date: May 30, 2024
    Inventor: An-Ping CHANG
  • Publication number: 20240178078
    Abstract: A control circuit is included in a first die of a stacked semiconductor device. The first die further includes a transistor that is electrically connected to the control circuit. The transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. In this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. This may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventor: Jen-Yuan CHANG
  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG