Abstract: There are provided a conductive paste composition for an internal electrode and a multilayer ceramic electronic component including the same. The conductive paste composition includes: 100 moles of a metal powder; 0.5 to 4.0 moles of a ceramic powder; and 0.03 to 0.1 mole of a silica (SiO2) powder. The conductive paste composition can raise the sintering shrinkage temperature of the internal electrodes and improve the connectivity of the internal electrodes, and can improve the degree of densification of the dielectric layer, thereby improving withstand voltage characteristics, reliability, and dielectric characteristics.

Abstract: There are provided a conductive paste composition for internal electrodes and a multilayer ceramic electronic component including the same. The conductive paste composition includes: a metal powder; and a refractory metal oxide powder having a smaller average grain diameter than the metal powder and a higher melting point than the metal powder. The conductive paste composition can raise the sintering shrinkage temperature of the internal electrodes and improve the connectivity of the internal electrodes.

Abstract: There is provided a multilayered ceramic electronic component capable of securing capacitance by controlling electrode connectivity. The multilayered ceramic electronic component includes: a ceramic main body; and internal electrodes formed in the interior of the ceramic main body and having a central portion and a tapered portion becoming thinner from the central portion toward edges thereof, respectively, wherein the ratio of the area of the tapered portion to the overall area of the internal electrodes is 35% or less. A desired capacitance can be obtained by controlling an electrode connectivity even in the small high capacitance multilayered ceramic capacitor.

Abstract: Disclosed herein is a conductive paste composition. The conductive paste composition according to the exemplary embodiment of the present invention includes a conductive powder including nickel or a nickel alloy; a spherical particulate inhibitor including BaTiO3 powders; and a glass composition having Chemical Formula of aLi2O-bK2O-cCaO-dBaO-eB2O3-fSiO2, wherein a, b, c, d, e, and f satisfy a+b+c+d+e+f=100, 2?a?10, 2?b?10, 0?c?25, 0?d?25, 5?e?20, and 50?f?80.

Abstract: A conductive paste composition for an internal electrode, and a multilayer ceramic capacitor (MLCC) including the same are provided. The conductive paste composition for an internal electrode includes: 100 parts by weight of metal powder particles; and 0.1 to 10 parts by weight of carbon nano-tubes (CNTs). The conductive paste composition for an internal electrode may control sintering shrinkage of metal powder particles.

Abstract: The fuse circuit includes a first program unit, a second program unit and a sensing circuit. The first and second program units are programmed simultaneously. The first program unit is programmed in a program mode in response to a fuse program signal and outputs a first signal in a sensing mode, such that the first signal increases when the first program unit is programmed. The second program unit is programmed in the program mode in response to the program signal and outputs a second signal in the sensing mode, such that the second signal decreases when the second program unit is programmed. The sensing circuit generates a sensing output signal in response to the first and second signals, such that the sensing output signal indicates whether or not the program units are programmed.

Abstract: A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.

Abstract: A system on chip includes a plurality of master devices, a plurality of slave devices that supply data in response to requests of the plurality of master devices and pointer update logic configured to process the requests from the plurality of master devices sequentially in a pipeline manner.

Abstract: An interface device includes a request queue and a request queue manager. The request queue includes multiple elements configured to receive corresponding requests from at least one master device and to indicate whether the corresponding requests are included using corresponding occupying bits. The request queue manager is configured to manage the request queue at least based on the occupying bits.

Abstract: An adhesive composition and an optical member using the same, the adhesive composition providing an adhesive having a storage modulus of about 8×105 to about 1×108 dyne/cm2 and a gel fraction of about 83% to about 95% as defined by Equation 1: Gel fraction (%)=(A/B)×100,??[Equation 1] in Equation 1, A is a mass measured after dissolving the adhesive at 23° C. for 48 hours in a solvent and then drying for 24 hours, and B is an initial mass.

Abstract: A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance.

Abstract: A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master. An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.

Abstract: Disclosed herein is a conductive paste composition. The conductive paste composition according to the exemplary embodiment of the present invention includes a conductive powder including nickel or a nickel alloy; a spherical particulate inhibitor including BaTiO3 powders; and a glass composition having Chemical Formula of aLi2O-bK2O-cCaO-dBaO-eB2O3-fSiO2, wherein a, b, c, d, e, and f satisfy a+b+c+d+e+f=100, 2?a?10, 2?b?10, 0?c?25, 0?d?25, 5?e?20, and 50?f?80.

Abstract: A bus system includes a master transferring write data internally via a first write data channel and an address internally via a first address channel; and a bus transferring the write data and the address to a slave from the master via one channel.

Abstract: A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the salve device.

Abstract: At least one example embodiment discloses a System on Chip (SoC). The SoC includes a master block, a plurality of slave blocks configured to operate in response to a request from the master block, and an interconnect block configured to deliver transactions occurring in the master block to the plurality of slave blocks through a plurality of transfer paths. The interconnect block is configured to monitor load information of the plurality of transfer paths and select one of the plurality of transfer paths according to the load information.

Abstract: A frequency measuring circuit and a semiconductor device having the frequency measuring circuit include a divided and shifted clock signal generator, a delayed clock signal generator and a phase detecting unit. The divided and shifted clock signal generator divides a frequency of a clock signal input from an exterior to output a frequency-divided clock signal, and delays the frequency-divided clock signal by a time proportional to a period of the clock signal to output a shifted clock signal. The delayed clock signal generator delays the frequency-divided clock signal by a fixed time to generate a plurality of delayed clock signals. The phase detecting unit receives the plurality of delayed clock signals and the shifted clock signal and detects a phase difference between each of the plurality of delayed clock signals and the shifted clock signal to output a plurality of phase detecting signals that represent information related to a frequency of the clock signal.

Abstract: Provided are a slimmer liquid crystal display (LCD) and a display apparatus set having the same. The LCD includes: a liquid crystal panel having sides; a light guide plate (LGP) which is overlapped by the liquid crystal panel; a container accommodating the LGP; a printed circuit board (PCB) which is disposed between the LGP and a sidewall of the container along one of the sides of the liquid crystal panel, and which is configured to provide an image signal to the liquid crystal panel; and a light source which is disposed between the LGP and a sidewall of the container along another one of the sides of the liquid crystal panel, and which is configured to provide light to the liquid crystal panel.

Abstract: The fuse circuit includes a first program unit, a second program unit and a sensing circuit. The first and second program units are programmed simultaneously. The first program unit is programmed in a program mode in response to a fuse program signal and outputs a first signal in a sensing mode, such that the first signal increases when the first program unit is programmed. The second program unit is programmed in the program mode in response to the program signal and outputs a second signal in the sensing mode, such that the second signal decreases when the second program unit is programmed. The sensing circuit generates a sensing output signal in response to the first and second signals, such that the sensing output signal indicates whether or not the program units are programmed.

Abstract: A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line driving signal to provide the first word-line driving signal to an array unit. The first sub word-line control signal generating circuit is disposed in the first region, and generates the first sub word-line control signal based on a sub word-line driving signal. Therefore, the memory core has a small size and, consequently so can the semiconductor device.