Patents by Inventor In Chul Jung

In Chul Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240049463
    Abstract: A single poly non-volatile memory device is provided. The single poly non-volatile memory device is formed in a semiconductor substrate, and includes a sensing transistor, a selection transistor, and a capacitor, wherein a thickness of a selection gate insulating film is formed to be thicker than a thickness of a sensing gate insulating film, wherein a thickness of a control gate insulating film of the capacitor is formed to be the same, or greater than, a thickness of the sensing gate insulating film, and wherein the sensing gate of the sensing transistor and the control gate of the capacitor are physically and electrically connected to each other.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 8, 2024
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Su Jin KIM, Min Kuck CHO, Jung Hwan LEE, In Chul JUNG
  • Patent number: 11825650
    Abstract: A single poly non-volatile memory device is provided. The single poly non-volatile memory device is formed in a semiconductor substrate, and includes a sensing transistor, a selection transistor, and a capacitor, wherein a thickness of a selection gate insulating film is formed to be thicker than a thickness of a sensing gate insulating film, wherein a thickness of a control gate insulating film of the capacitor is formed to be the same, or greater than, a thickness of the sensing gate insulating film, and wherein the sensing gate of the sensing transistor and the control gate of the capacitor are physically and electrically connected to each other.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: November 21, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Su Jin Kim, Min Kuck Cho, Jung Hwan Lee, In Chul Jung
  • Publication number: 20230059628
    Abstract: A semiconductor device includes: a logic region and a non-volatile memory (NVM) region; a logic gate insulating film disposed on a substrate in the logic region; at least one gate oxidation acceleration ion implantation layer disposed in the NVM region; at least one NVM gate insulating film disposed on the at least one gate oxidation acceleration ion implantation layer; a logic gate electrode disposed on the logic gate insulating film; and at least one NVM gate electrode disposed on the at least one NVM gate insulating film, wherein a thickness of the at least one NVM gate insulating film is equal or greater than a thickness of the logic gate insulating film.
    Type: Application
    Filed: May 13, 2022
    Publication date: February 23, 2023
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Su Jin KIM, Min Kuck CHO, Jung Hwan LEE, In Chul JUNG
  • Publication number: 20230053444
    Abstract: A single poly non-volatile memory device is provided. The single poly non-volatile memory device is formed in a semiconductor substrate, and includes a sensing transistor, a selection transistor, and a capacitor, wherein a thickness of a selection gate insulating film is formed to be thicker than a thickness of a sensing gate insulating film, wherein a thickness of a control gate insulating film of the capacitor is formed to be the same, or greater than, a thickness of the sensing gate insulating film, and wherein the sensing gate of the sensing transistor and the control gate of the capacitor are physically and electrically connected to each other.
    Type: Application
    Filed: December 29, 2021
    Publication date: February 23, 2023
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Su Jin KIM, Min Kuck CHO, Jung Hwan LEE, In Chul JUNG
  • Patent number: 10985074
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 20, 2021
    Assignee: Key Foundry Co., Ltd
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Patent number: 10867677
    Abstract: A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: December 15, 2020
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Su Jin Kim, Myeong Seok Kim, In Chul Jung, Young Bae Kim, Seung Guk Kim, Jung Hwan Lee
  • Patent number: 10685953
    Abstract: An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 16, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Hyun Chul Kim, Hee Baeg An, In Chul Jung, Jung Hwan Lee, Kyung Ho Lee
  • Patent number: 10453755
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 22, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Publication number: 20190237140
    Abstract: A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.
    Type: Application
    Filed: September 6, 2018
    Publication date: August 1, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Su Jin KIM, Myeong Seok KIM, In Chul JUNG, Young Bae KIM, Seung Guk KIM, Jung Hwan LEE
  • Publication number: 20190195573
    Abstract: A printed circuit-type heat exchanger includes a vaporizer having a structure in which one or more A-channel plates and one or more B-channel plates are sequentially stacked, to vaporize a fluid A with heat exchange through the A-fluid channels. A gas-liquid separator separates the fluid A into a vaporized gas and a non-vaporized liquid and includes a gas outlet for the vaporized gas and a liquid outlet for non-vaporized liquid. A super heater, having the same structure as the vaporizer, super heats the vaporized gas with heat exchange through the A-fluid channels and discharges the superheated gas through a gas outlet communicating with the outside. A first intermediate plate is disposed between the vaporizer and the gas-liquid separator to separate the vaporizer from the gas-liquid separator, and a second intermediate plate is disposed between the gas-liquid separator and the super heater to separate the super heater from the gas-liquid separator.
    Type: Application
    Filed: November 8, 2018
    Publication date: June 27, 2019
    Inventors: Ki Hoon YANG, Jeong Kil KIM, Chil Yeong SEON, In Chul JUNG
  • Publication number: 20190198401
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Application
    Filed: January 25, 2019
    Publication date: June 27, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Min Kuck CHO, Myeong Seok KIM, In Chul JUNG
  • Publication number: 20190137197
    Abstract: A heat exchanger includes a stack of channel plates including first and second channel plates alternately stacked on one another such that fluids A and B are heat-exchanged each other. The first channel plate has a fluid path for fluid A on one surface thereof, wherein inflow and outflow parts for fluid A are formed on the fluid path for fluid A, and the second channel plate has a fluid path for fluid B intersecting with the fluid path for fluid A on one surface thereof. The first channel plate has communicating structures corresponding to the inflow and outflow parts for fluid B. The heat exchanger also includes an upper plate section attached to an upper surface of the stack, and a lower plate section attached to an undersurface of the stack.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 9, 2019
    Applicant: Doosan Heavy Industries & Construction Co., LTD
    Inventors: Ki Hoon Yang, Jeong Kil Kim, Chil Yeong Seon, In Chul Jung
  • Publication number: 20180350696
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Min Kuck CHO, Myeong Seok KIM, In Chul JUNG
  • Publication number: 20180342497
    Abstract: An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.
    Type: Application
    Filed: July 17, 2018
    Publication date: November 29, 2018
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Hyun Chul KIM, Hee Baeg AN, In Chul JUNG, Jung Hwan LEE, Kyung Ho LEE
  • Patent number: 10074644
    Abstract: An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: September 11, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Hyun Chul Kim, Hee Baeg An, In Chul Jung, Jung Hwan Lee, Kyung Ho Lee
  • Patent number: 10062616
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: August 28, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Patent number: 10055408
    Abstract: A method of extracting an important keyword by an important keyword extracting server, the method includes receiving a set of one or more documents from a network, receiving one or more user defined keywords from a user terminal, calculating, by the server, a relative importance value for each of words detected in the set of documents, determining, by the server, a weight for each of the words based on the one or more user defined keywords, applying, by the server, the weight for each of the words to the relative importance value for each of the words, determining, by the server, at least one of the words to be the important keyword based on the relative importance value to which the weight is applied and transmitting, by the server, the important keyword to the user terminal. Therefore, the method may effectively detect a user defined keyword from at least one document.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: August 21, 2018
    Assignee: LG CNS CO., LTD.
    Inventors: Seen Tae Lee, Hyun Pyo Kim, Jae Man Kim, Sun Min Yun, Cho Rong Yoon, Yoo Jin Chang, In Chul Jung, Tae Chang Jee
  • Publication number: 20180182747
    Abstract: An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.
    Type: Application
    Filed: August 24, 2017
    Publication date: June 28, 2018
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Hyun Chul KIM, Hee Baeg AN, In Chul JUNG, Jung Hwan LEE, Kyung Ho LEE
  • Publication number: 20180025948
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Application
    Filed: December 23, 2016
    Publication date: January 25, 2018
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Min Kuck CHO, Myeong Seok KIM, In Chul JUNG
  • Patent number: 9582486
    Abstract: A document classification and analysis system includes a processor, a memory including one or more storage regions, and a non-transitory computer-readable medium having stored thereon instructions that, when executed, cause the processor to perform a method. The method includes receiving a document including a plurality of words, performing morpheme analysis on the document to extract original forms of the words, tagging each of the words based on a corresponding part-of-speech, determining location information of the words based on an order of the words in the document, applying one or more lexicon lists to the document to classify each of the words, and storing the location information.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: February 28, 2017
    Assignee: LC CNS CO., LTD.
    Inventors: In Chul Jung, JaeMan Kim, Hyunpyo Kim, Sunmin Yun, Chorong Yoon, Seentae Lee, Yoo Jin Chang, Tae-Chang Jee