Abstract: A circuit board includes an insulation part, a support layer disposed on the insulation part, a metal case disposed in the insulation part, a heat-exchanging fluid distributed within the enclosed space, and a first porous material distributed within the enclosed space. The metal case is thermally coupled to the support layer and includes a first inner surface, a second inner surface opposite to the first inner surface and positioned between the first inner surface and the support layer, a third inner surface connecting the first inner surface and the second inner surface, and an enclosed space surrounded by the first inner surface, the second inner surface and the third inner surface. The first porous material is disposed on the first inner surface.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.

Abstract: A resistive random-access memory (RRAM) device, including a bottom electrode, a high work function layer, a resistive material layer and a top electrode sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part, first spacers covering sidewalls of the top part and the top electrode, and second spacers covering sidewalls of the bottom part, thereby constituting a RRAM cell.

Abstract: A central unit of a base station receives, from a distributed unit of the base station, a network slice group identifier of a network slice group, and at least one parameter indicating that the network slice group comprises one or more network slices, wherein the at least one parameter comprises one or more network slice identifiers indicating the one or more network slices. The central unit of the base station sends, to a wireless device, a radio resource control (RRC) information message comprising the network slice group identifier.

Abstract: The present disclosure provides a light-emitting module and a display apparatus thereof. The light-emitting module includes a circuit substrate which includes a first surface and a second surface opposite to the first surface. The first surface includes a plurality of conductive channels, and the second surface includes a plurality of conductive pads. A plurality of light-emitting groups is arranged in a matrix on the first surface. Each of the light-emitting groups includes a red light-emitting diode chip, a green light-emitting diode chip, and a blue light-emitting diode chip. An electric component is disposed on the first surface and located in the light-emitting groups matrix. A translucent encapsulating component covers the plurality of light-emitting groups and the electric component. Wherein, the light-emitting groups matrix comprises m columns and n rows.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine that the UE is connected to a wireless network on a first carrier frequency in a first frequency range that is associated with a lower data rate than a second carrier frequency in a second frequency range. In some aspects, the first frequency range may be associated with a first version of a radio access technology (RAT) and the second frequency range may be associated with a second version of the RAT. The UE may determine a bandwidth metric associated with the first carrier frequency in the first frequency range. The UE may display a first visual indicator associated with the first version of the RAT or a second visual indicator associated with the second version of the RAT based on the bandwidth metric. Numerous other aspects are described.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes second spacers over the semiconductor fin. The second spacers vertically extend farther from the semiconductor fin than the first spacers. The semiconductor device includes a metal gate over the semiconductor fin, the metal gate is sandwiched by the first spacers. The metal gate includes a glue layer that contains tantalum nitride.

Abstract: Aspects of this disclosure relate to an elastic wave device. The elastic wave device includes a sub-wavelength thick piezoelectric layer, an interdigital transducer electrode on the piezoelectric layer, and a high velocity layer configured to inhibit an elastic wave from leaking from the piezoelectric layer at anti-resonance.

Abstract: A buckle locking structure device for a rear compartment cover of a pickup truck includes: a cross rod aluminum extrusion (1); a slider (2); a T-rod (3); a buckle block (4); a handle (5); a T-insertion block (7); and a frame body aluminum extrusion (8); a lug (403) provided center of a bottom surface of the buckle block (4); left and right semi-circular arc flanges (4031) provided on the center of the bottom surface of the buckle block (4) on a and to left and right sides of the lug (403), respectively; a left edge part slot (5031) extending towards lug (403) and being engageable with the left semi-circular arc flange (4031) of the buckle block (4) so that the left edge part slot (5031) slides on the left semi-circular arc flange (4031) of the buckle block (4) for fastening.

Abstract: A conductive polyester composition is provided, which includes a polyester base material and a conductive reinforcing material. The conductive reinforcing material includes a plurality of carbon nanotubes, and the plurality of carbon nanotubes are dispersed in the polyester base material. In each of the carbon nanotubes, a length of the carbon nanotube is defined as L, a diameter of the carbon nanotube is defined as D and is between 1 nanometer and 30 nanometers, and an L/D value of the carbon nanotube is between 300 and 2,000. The plurality of carbon nanotubes are in contact with each other to form a plurality of contact points, so that the conductive polyester composition has a surface impedance of not greater than 107 ?/sq.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: An electronic device includes a conductive structure, a first insulation layer and a second insulation layer. The first insulation layer is disposed on the conductive structure. The second insulation layer is disposed on the first insulation layer. The first insulation layer includes a first hole, and the first hole overlaps a part of the conductive structure. The second insulation layer includes a second hole, and the first hole and the second hole at least partially overlap. A width of the second hole is less than a width of the first hole.

Abstract: A trim assembly for a regulator can include a cage and a plug assembly. The cage can include a peripheral wall defining an opening and a plurality of cage apertures formed in the peripheral wall. The plug assembly can include a plug and a sealing element and can be configured to be moveably received within the opening so that the sealing element contacts an inner surface of the cage to vary a flow area through the plurality of cage apertures depending on the position of the plug.

Abstract: A testing device for testing an integrated circuit package is provided, including a printed circuit board, a testing socket, a conductive fastener, a cover, and a conductive element assembly. The printed circuit board includes a first metal layer formed on the bottom surface thereof. The testing socket is disposed above the printed circuit board. The conductive fastener is configured to secure the testing socket to the printed circuit board, wherein the conductive fastener is electrically connected to the first metal layer and the testing socket. The cover is disposed above the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket, wherein the cover makes electrical contact with the integrated circuit package. The conductive element assembly is disposed between and electrically connected to the cover and the testing socket.