Abstract: A method for patterning a stack having a patterned organic mask with a plurality of mask features including sidewalls and tops, a hardmask and an etch layer, wherein the patterned organic mask is positioned over the hardmask which is positioned over the etch layer is provided. An atomic layer deposition is deposited, wherein the depositing the atomic layer deposition controllably trims the plurality of mask features of the patterned organic mask. The atomic layer deposition is broken through. The hardmask is selectively etched with respect to the patterned organic mask, wherein the atomic layer deposition reduces faceting of the plurality of mask features of the patterned organic mask during the selective etching.

Abstract: A method for forming a stair-step structure in a substrate within a plasma processing chamber is provided. An organic mask is formed over the substrate. The organic mask is trimmed with a vertical to lateral ratio of less than 0.8, wherein the trimming simultaneously forms a deposition over the organic mask. The substrate is etched. The steps of trimming the organic mask and etching the substrate are cyclically repeated a plurality of times.

Abstract: A method for forming a stair-step structure in a substrate within a plasma processing chamber is provided. An organic mask is formed over the substrate. The organic mask is trimmed with a vertical to lateral ratio of less than 0.8, wherein the trimming simultaneously forms a deposition over the organic mask. The substrate is etched. The steps of trimming the organic mask and etching the substrate are cyclically repeated a plurality of times.

Abstract: A method for selectively etching a high-k dielectric layer with respect to a polysilicon material is provided. The high-k dielectric layer is partially removed by Ar sputtering, and then the high-k dielectric layer is etched using an etching gas comprising BCl3. The high-k dielectric layer and the polysilicon material may be formed on a substrate. In order to partially remove the high-k dielectric layer, a sputtering gas containing Ar is provided into an etch chamber in which the substrate is placed, a plasma is generated from the sputtering gas, and then the sputtering gas is stopped. In order to etch the high-k dielectric layer, the etching gas is provided into the etch chamber, a plasma is generated from the etching gas, and then the etching gas is stopped.

Abstract: A method for selectively etching a high-k dielectric layer with respect to a polysilicon material is provided. The high-k dielectric layer is partially removed by Ar sputtering, and then the high-k dielectric layer is etched using an etching gas comprising BCl3. The high-k dielectric layer and the polysilicon material may be formed on a substrate. In order to partially remove the high-k dielectric layer, a sputtering gas containing Ar is provided into an etch chamber in which the substrate is placed, a plasma is generated from the sputtering gas, and then the sputtering gas is stopped. In order to etch the high-k dielectric layer, the etching gas is provided into the etch chamber, a plasma is generated from the etching gas, and then the etching gas is stopped.

Abstract: Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure on the substrate that extends laterally in a second direction to cover a portion of the active pattern and a conductive layer that is on at least portions of side surfaces of the active pattern that are adjacent a side portion of the gate structure. The conductive layer may comprise a semiconductor layer, and the semiconductor layer may be in electrical contact with a contact pad. In other embodiments, the conductive layer may comprise a contact pad.

Abstract: A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.

Abstract: Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure on the substrate that extends laterally in a second direction to cover a portion of the active pattern and a conductive layer that is on at least portions of side surfaces of the active pattern that are adjacent a side portion of the gate structure. The conductive layer may comprise a semiconductor layer, and the semiconductor layer may be in electrical contact with a contact pad. In other embodiments, the conductive layer may comprise a contact pad.

Abstract: A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.